Promotes 5 Thumb-mode bare-metal Arm targets to Tier 2#155763
Promotes 5 Thumb-mode bare-metal Arm targets to Tier 2#155763cezarbbb wants to merge 1 commit intorust-lang:mainfrom
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Some changes occurred in src/doc/rustc/src/platform-support cc @Noratrieb These commits modify compiler targets. |
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r? @adwinwhite rustbot has assigned @adwinwhite. Use Why was this reviewer chosen?The reviewer was selected based on:
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Blocked on rust-lang/compiler-team#985. |
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@rustbot ping arm-maintainers |
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Error: Only Rust team members can ping teams. Please file an issue on GitHub at triagebot if there's a problem with this bot, or reach out on #triagebot on Zulip. |
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@rustbot ping arm-maintainers |
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Error: This team ( Please file an issue on GitHub at triagebot if there's a problem with this bot, or reach out on #triagebot on Zulip. |
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arm-maintainers said yes over on rust-lang/compiler-team#985 (comment) (just for anyone else looking at this without looking at that thread first) |
This PR promotes five Thumb-mode bare-metal Arm targets to Tier 2, joining their Arm-mode counterparts which are already Tier 2:
thumbv7a-none-eabiarmv7a-none-eabithumbv7a-none-eabihfarmv7a-none-eabihfthumbv7r-none-eabiarmv7r-none-eabithumbv7r-none-eabihfarmv7r-none-eabihfthumbv8r-none-eabihfarmv8r-none-eabihfNote: There is no
thumbv8r-none-eabitarget because the Cortex-R52 processor always includes an FPU, making a soft-float ABI variant unnecessary.These Thumb-mode targets generate T32 code by default while their Arm-mode counterparts generate A32 code. They share the same LLVM backend, ABI, and data layout — the only spec differences are the
llvm_targetstring and the description.See rust-lang/compiler-team#985