Compiling this code (Godbolt)

#![no_std]
use core::sync::atomic::{AtomicU32, Ordering};

#[panic_handler]
fn panic_handler(_: &core::panic::PanicInfo<'_>) -> ! {
    loop {}
}

static COUNTER: AtomicU32 = AtomicU32::new(0);

#[unsafe(no_mangle)]
fn atomic_load_acquire() -> u32 {
    COUNTER.load(Ordering::Acquire)
}

#[unsafe(no_mangle)]
fn atomic_store_release(val : u32) {
    COUNTER.store(val, Ordering::Release)
}

results in the following LLVM error for target CPUs below sm_70:
rustc-LLVM ERROR: PTX does not support "atomic" for orderings different than"NotAtomic" or "Monotonic" for sm_60 or older, but order is: "acquire".

Atomic ordering support was added with sm_70 and ptx60. Therefore, it is expected that these instructions can not be produced by LLVM.

However, this is somewhat similar to e.g. Release or AcqRelease orderings for atomic loads in general, where we panic instead of producing an LLVM error.
So I would assume, we should also panic in the above case and not produce an LLVM error.