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Rollup merge of #145531 - sayantn:detect-apxf-avx10, r=Amanieu
Add runtime detection for APX-F and AVX10 This was missed in #139534 and #139675 `@rustbot` label O-x86_64 O-x86_32 A-target-feature r? `@Amanieu`
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‎library/std_detect/src/detect/arch/x86.rs‎

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@@ -233,6 +233,12 @@ features! {
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/// AMX-TF32 (TensorFloat32 Operations)
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@FEATURE: #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] amx_transpose: "amx-transpose";
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/// AMX-TRANSPOSE (Matrix Transpose Operations)
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@FEATURE: #[unstable(feature = "apx_target_feature", issue = "139284")] apxf: "apxf";
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/// APX-F (Advanced Performance Extensions - Foundation)
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@FEATURE: #[unstable(feature = "avx10_target_feature", issue = "138843")] avx10_1: "avx10.1";
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/// AVX10.1
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@FEATURE: #[unstable(feature = "avx10_target_feature", issue = "138843")] avx10_2: "avx10.2";
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/// AVX10.2
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@FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] f16c: "f16c";
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/// F16C (Conversions between IEEE-754 `binary16` and `binary32` formats)
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@FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] fma: "fma";

‎library/std_detect/src/detect/os/x86.rs‎

Lines changed: 41 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -137,6 +137,32 @@ pub(crate) fn detect_features() -> cache::Initializer {
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enable(ebx, 2, Feature::widekl);
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}
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// This detects ABM on AMD CPUs and LZCNT on Intel CPUs.
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// On intel CPUs with popcnt, lzcnt implements the
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// "missing part" of ABM, so we map both to the same
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// internal feature.
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//
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// The `is_x86_feature_detected!("lzcnt")` macro then
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// internally maps to Feature::abm.
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enable(extended_proc_info_ecx, 5, Feature::lzcnt);
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// As Hygon Dhyana originates from AMD technology and shares most of the architecture with
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// AMD's family 17h, but with different CPU Vendor ID("HygonGenuine")/Family series
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// number(Family 18h).
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//
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// For CPUID feature bits, Hygon Dhyana(family 18h) share the same definition with AMD
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// family 17h.
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//
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// Related AMD CPUID specification is https://www.amd.com/system/files/TechDocs/25481.pdf.
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// Related Hygon kernel patch can be found on
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// http://lkml.kernel.org/r/5ce86123a7b9dad925ac583d88d2f921040e859b.1538583282.git.puwen@hygon.cn
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if vendor_id == *b"AuthenticAMD" || vendor_id == *b"HygonGenuine" {
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// These features are available on AMD arch CPUs:
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enable(extended_proc_info_ecx, 6, Feature::sse4a);
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enable(extended_proc_info_ecx, 21, Feature::tbm);
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enable(extended_proc_info_ecx, 11, Feature::xop);
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}
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// `XSAVE` and `AVX` support:
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let cpu_xsave = bit::test(proc_info_ecx as usize, 26);
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if cpu_xsave {
@@ -161,6 +187,7 @@ pub(crate) fn detect_features() -> cache::Initializer {
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// * AVX -> `XCR0.AVX[2]`
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// * AVX-512 -> `XCR0.AVX-512[7:5]`.
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// * AMX -> `XCR0.AMX[18:17]`
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// * APX -> `XCR0.APX[19]`
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//
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// by setting the corresponding bits of `XCR0` to `1`.
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//
@@ -173,6 +200,8 @@ pub(crate) fn detect_features() -> cache::Initializer {
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let os_avx512_support = xcr0 & 0xe0 == 0xe0;
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// Test `XCR0.AMX[18:17]` with the mask `0b110_0000_0000_0000_0000 == 0x60000`
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let os_amx_support = xcr0 & 0x60000 == 0x60000;
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// Test `XCR0.APX[19]` with the mask `0b1000_0000_0000_0000_0000 == 0x80000`
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let os_apx_support = xcr0 & 0x80000 == 0x80000;
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// Only if the OS and the CPU support saving/restoring the AVX
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// registers we enable `xsave` support:
@@ -262,33 +291,20 @@ pub(crate) fn detect_features() -> cache::Initializer {
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enable(amx_feature_flags_eax, 8, Feature::amx_movrs);
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}
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}
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}
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}
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// This detects ABM on AMD CPUs and LZCNT on Intel CPUs.
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// On intel CPUs with popcnt, lzcnt implements the
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// "missing part" of ABM, so we map both to the same
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// internal feature.
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//
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// The `is_x86_feature_detected!("lzcnt")` macro then
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// internally maps to Feature::abm.
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enable(extended_proc_info_ecx, 5, Feature::lzcnt);
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if os_apx_support {
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enable(extended_features_edx_leaf_1, 21, Feature::apxf);
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}
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// As Hygon Dhyana originates from AMD technology and shares most of the architecture with
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// AMD's family 17h, but with different CPU Vendor ID("HygonGenuine")/Family series
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// number(Family 18h).
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//
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// For CPUID feature bits, Hygon Dhyana(family 18h) share the same definition with AMD
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// family 17h.
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//
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// Related AMD CPUID specification is https://www.amd.com/system/files/TechDocs/25481.pdf.
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// Related Hygon kernel patch can be found on
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// http://lkml.kernel.org/r/5ce86123a7b9dad925ac583d88d2f921040e859b.1538583282.git.puwen@hygon.cn
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if vendor_id == *b"AuthenticAMD" || vendor_id == *b"HygonGenuine" {
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// These features are available on AMD arch CPUs:
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enable(extended_proc_info_ecx, 6, Feature::sse4a);
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enable(extended_proc_info_ecx, 21, Feature::tbm);
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enable(extended_proc_info_ecx, 11, Feature::xop);
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let avx10_1 = enable(extended_features_edx_leaf_1, 19, Feature::avx10_1);
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if avx10_1 {
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let CpuidResult { ebx, .. } = unsafe { __cpuid(0x24) };
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let avx10_version = ebx & 0xff;
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if avx10_version >= 2 {
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value.set(Feature::avx10_2 as u32);
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}
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}
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}
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}
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}
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