Rollup merge of #146134 - maurer:nvptx-sync, r=durin42

Zalathar · web-flow · commit a1469aadc2e7 · 2025-09-04T10:02:02.000+10:00
llvm: nvptx: Layout update to match LLVM

LLVM upstream switched layouts to support 256-bit vector load/store.

``````@rustbot`````` label llvm-main

r? durin42
diff --git a/compiler/rustc_codegen_llvm/src/context.rs b/compiler/rustc_codegen_llvm/src/context.rs
@@ -217,6 +217,10 @@ pub(crate) unsafe fn create_module<'ll>(
             // LLVM 22.0 updated the default layout on avr: https://github.com/llvm/llvm-project/pull/153010
             target_data_layout = target_data_layout.replace("n8:16", "n8")
         }
+        if sess.target.arch == "nvptx64" {
+            // LLVM 22 updated the NVPTX layout to indicate 256-bit vector load/store: https://github.com/llvm/llvm-project/pull/155198
+            target_data_layout = target_data_layout.replace("-i256:256", "");
+        }
     }
 
     // Ensure the data-layout values hardcoded remain the defaults.
diff --git a/compiler/rustc_target/src/spec/targets/nvptx64_nvidia_cuda.rs b/compiler/rustc_target/src/spec/targets/nvptx64_nvidia_cuda.rs
@@ -6,7 +6,7 @@ use crate::spec::{
 pub(crate) fn target() -> Target {
     Target {
         arch: "nvptx64".into(),
-        data_layout: "e-p6:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64".into(),
+        data_layout: "e-p6:32:32-i64:64-i128:128-i256:256-v16:16-v32:32-n16:32:64".into(),
         llvm_target: "nvptx64-nvidia-cuda".into(),
         metadata: TargetMetadata {
             description: Some("--emit=asm generates PTX code that runs on NVIDIA GPUs".into()),

Original file line number	Diff line number	Diff line change
`@@ -217,6 +217,10 @@ pub(crate) unsafe fn create_module<'ll>(`
`217`	`217`	`// LLVM 22.0 updated the default layout on avr: https://github.com/llvm/llvm-project/pull/153010`
`218`	`218`	`target_data_layout = target_data_layout.replace("n8:16", "n8")`
`219`	`219`	`}`
	`220`	`+ if sess.target.arch == "nvptx64" {`
	`221`	`+ // LLVM 22 updated the NVPTX layout to indicate 256-bit vector load/store: https://github.com/llvm/llvm-project/pull/155198`
	`222`	`+ target_data_layout = target_data_layout.replace("-i256:256", "");`
	`223`	`+ }`
`220`	`224`	`}`
`221`	`225`
`222`	`226`	`// Ensure the data-layout values hardcoded remain the defaults.`