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Auto merge of #131341 - taiki-e:ppc-clobber-abi, r=bzEq,workingjubilee
Support clobber_abi and vector registers (clobber-only) in PowerPC inline assembly This supports `clobber_abi` which is one of the requirements of stabilization mentioned in #93335. This basically does a similar thing I did in #130630 to implement `clobber_abi` for s390x, but for powerpc/powerpc64/powerpc64le. - This also supports vector registers (as `vreg`) as clobber-only, which need to support clobbering of them to implement `clobber_abi`. - `vreg` should be able to accept `#[repr(simd)]` types as input/output if the unstable `altivec` target feature is enabled, but `core::arch::{powerpc,powerpc64}` vector types, `#[repr(simd)]`, and `core::simd` are all unstable, so the fact that this is currently a clobber-only should not be considered a blocker of clobber_abi implementation or stabilization. So I have not implemented it in this PR. - See #131551 (which is based on this PR) for a PR to implement this. - (I'm not sticking to whether that PR should be a separate PR or part of this PR, so I can merge that PR into this PR if needed.) Refs: - PPC32 SysV: Section "Function Calling Sequence" in [System V Application Binary Interface PowerPC Processor Supplement](https://refspecs.linuxfoundation.org/elf/elfspec_ppc.pdf) - PPC64 ELFv1: Section 3.2 "Function Calling Sequence" in [64-bit PowerPC ELF Application Binary Interface Supplement](https://refspecs.linuxfoundation.org/ELF/ppc64/PPC-elf64abi.html#FUNC-CALL) - PPC64 ELFv2: Section 2.2 "Function Calling Sequence" in [64-Bit ELF V2 ABI Specification](https://openpowerfoundation.org/specifications/64bitelfabi/) - AIX: [Register usage and conventions](https://www.ibm.com/docs/en/aix/7.3?topic=overview-register-usage-conventions), [Special registers in the PowerPC®](https://www.ibm.com/docs/en/aix/7.3?topic=overview-special-registers-in-powerpc), [AIX vector programming](https://www.ibm.com/docs/en/aix/7.3?topic=concepts-aix-vector-programming) - Register definition in LLVM: https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/PowerPC/PPCRegisterInfo.td#L189 If I understand the above four ABI documentations correctly, except for the PPC32 SysV's VR (Vector Registers) and 32-bit AIX (currently not supported by rustc)'s r13, there does not appear to be important differences in terms of implementing `clobber_abi`: - The above four ABIs are consistent about FPR (0-13: volatile, 14-31: nonvolatile), CR (0-1,5-7: volatile, 2-4: nonvolatile), XER (volatile), and CTR (volatile). - As for GPR, only the registers we are treating as reserved are slightly different - r0, r3-r12 are volatile - r1(sp, reserved), r14-31 are nonvolatile - r2(reserved) is TOC pointer in PPC64 ELF/AIX, system-reserved register in PPC32 SysV (AFAIK used as thread pointer in Linux/BSDs) - r13(reserved for non-32-bit-AIX) is thread pointer in PPC64 ELF, small data area pointer register in PPC32 SysV, "reserved under 64-bit environment; not restored across system calls[^r13]" in AIX) - As for FPSCR, volatile in PPC64 ELFv1/AIX, some fields are volatile only in certain situations (rest are volatile) in PPC32 SysV/PPC64 ELFv2. - As for VR (Vector Registers), it is not mentioned in PPC32 SysV, v0-v19 are volatile in both in PPC64 ELF/AIX, v20-v31 are nonvolatile in PPC64 ELF, reserved or nonvolatile depending on the ABI ([vec-extabi vs vec-default in LLVM](https://reviews.llvm.org/D89684), we are [using vec-extabi](#131341 (comment))) in AIX: > When the default Vector enabled mode is used, these registers are reserved and must not be used. > In the extended ABI vector enabled mode, these registers are nonvolatile and their values are preserved across function calls I left [FIXME comment about PPC32 SysV](#131341 (comment)) and added ABI check for AIX. - As for VRSAVE, it is not mentioned in PPC32 SysV, nonvolatile in PPC64 ELFv1, reserved in PPC64 ELFv2/AIX - As for VSCR, it is not mentioned in PPC32 SysV/PPC64 ELFv1, some fields are volatile only in certain situations (rest are volatile) in PPC64 ELFv2, volatile in AIX We are currently treating r1-r2, r13 (non-32-bit-AIX), r29-r31, LR, CTR, and VRSAVE as reserved. We are currently not processing anything about FPSCR and VSCR, but I feel those are things that should be processed by `preserves_flags` rather than `clobber_abi` if we need to do something about them. (However, PPCRegisterInfo.td in LLVM does not seem to define anything about them.) Replaces #111335 and #124279 cc `@ecnelises` `@bzEq` `@lu-zero` r? `@Amanieu` `@rustbot` label +O-PowerPC +A-inline-assembly [^r13]: callee-saved, according to [LLVM](https://github.com/llvm/llvm-project/blob/6a6af0246bd2d68291582e9aefc0543e5c6102fe/llvm/lib/Target/PowerPC/PPCCallingConv.td#L322) and [GCC](https://github.com/gcc-mirror/gcc/blob/a9173a50e7e346a218323916e4d3add8552529ae/gcc/config/rs6000/rs6000.h#L859).
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‎compiler/rustc_codegen_gcc/src/asm.rs

+4-2
Original file line numberDiff line numberDiff line change
@@ -654,7 +654,8 @@ fn reg_to_gcc(reg: InlineAsmRegOrRegClass) -> ConstraintOrRegister {
654654
InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::reg_nonzero) => "b",
655655
InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::freg) => "f",
656656
InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::cr)
657-
| InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::xer) => {
657+
| InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::xer)
658+
| InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::vreg) => {
658659
unreachable!("clobber-only")
659660
}
660661
InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg) => "r",
@@ -729,7 +730,8 @@ fn dummy_output_type<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, reg: InlineAsmRegCl
729730
InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::reg_nonzero) => cx.type_i32(),
730731
InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::freg) => cx.type_f64(),
731732
InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::cr)
732-
| InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::xer) => {
733+
| InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::xer)
734+
| InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::vreg) => {
733735
unreachable!("clobber-only")
734736
}
735737
InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg) => cx.type_i32(),

‎compiler/rustc_codegen_llvm/src/asm.rs

+6-2
Original file line numberDiff line numberDiff line change
@@ -638,7 +638,9 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass, layout: Option<&TyAndLayout<'_>>) ->
638638
PowerPC(PowerPCInlineAsmRegClass::reg) => "r",
639639
PowerPC(PowerPCInlineAsmRegClass::reg_nonzero) => "b",
640640
PowerPC(PowerPCInlineAsmRegClass::freg) => "f",
641-
PowerPC(PowerPCInlineAsmRegClass::cr) | PowerPC(PowerPCInlineAsmRegClass::xer) => {
641+
PowerPC(PowerPCInlineAsmRegClass::cr)
642+
| PowerPC(PowerPCInlineAsmRegClass::xer)
643+
| PowerPC(PowerPCInlineAsmRegClass::vreg) => {
642644
unreachable!("clobber-only")
643645
}
644646
RiscV(RiscVInlineAsmRegClass::reg) => "r",
@@ -800,7 +802,9 @@ fn dummy_output_type<'ll>(cx: &CodegenCx<'ll, '_>, reg: InlineAsmRegClass) -> &'
800802
PowerPC(PowerPCInlineAsmRegClass::reg) => cx.type_i32(),
801803
PowerPC(PowerPCInlineAsmRegClass::reg_nonzero) => cx.type_i32(),
802804
PowerPC(PowerPCInlineAsmRegClass::freg) => cx.type_f64(),
803-
PowerPC(PowerPCInlineAsmRegClass::cr) | PowerPC(PowerPCInlineAsmRegClass::xer) => {
805+
PowerPC(PowerPCInlineAsmRegClass::cr)
806+
| PowerPC(PowerPCInlineAsmRegClass::xer)
807+
| PowerPC(PowerPCInlineAsmRegClass::vreg) => {
804808
unreachable!("clobber-only")
805809
}
806810
RiscV(RiscVInlineAsmRegClass::reg) => cx.type_i32(),

‎compiler/rustc_target/src/asm/mod.rs

+30
Original file line numberDiff line numberDiff line change
@@ -893,6 +893,7 @@ pub enum InlineAsmClobberAbi {
893893
Arm64EC,
894894
RiscV,
895895
LoongArch,
896+
PowerPC,
896897
S390x,
897898
Msp430,
898899
}
@@ -944,6 +945,10 @@ impl InlineAsmClobberAbi {
944945
"C" | "system" => Ok(InlineAsmClobberAbi::LoongArch),
945946
_ => Err(&["C", "system"]),
946947
},
948+
InlineAsmArch::PowerPC | InlineAsmArch::PowerPC64 => match name {
949+
"C" | "system" => Ok(InlineAsmClobberAbi::PowerPC),
950+
_ => Err(&["C", "system"]),
951+
},
947952
InlineAsmArch::S390x => match name {
948953
"C" | "system" => Ok(InlineAsmClobberAbi::S390x),
949954
_ => Err(&["C", "system"]),
@@ -1121,6 +1126,31 @@ impl InlineAsmClobberAbi {
11211126
f16, f17, f18, f19, f20, f21, f22, f23,
11221127
}
11231128
},
1129+
InlineAsmClobberAbi::PowerPC => clobbered_regs! {
1130+
PowerPC PowerPCInlineAsmReg {
1131+
// r0, r3-r12
1132+
r0,
1133+
r3, r4, r5, r6, r7,
1134+
r8, r9, r10, r11, r12,
1135+
1136+
// f0-f13
1137+
f0, f1, f2, f3, f4, f5, f6, f7,
1138+
f8, f9, f10, f11, f12, f13,
1139+
1140+
// v0-v19
1141+
// FIXME: PPC32 SysV ABI does not mention vector registers processing.
1142+
// https://refspecs.linuxfoundation.org/elf/elfspec_ppc.pdf
1143+
v0, v1, v2, v3, v4, v5, v6, v7,
1144+
v8, v9, v10, v11, v12, v13, v14,
1145+
v15, v16, v17, v18, v19,
1146+
1147+
// cr0-cr1, cr5-cr7, xer
1148+
cr0, cr1,
1149+
cr5, cr6, cr7,
1150+
xer,
1151+
// lr and ctr are reserved
1152+
}
1153+
},
11241154
InlineAsmClobberAbi::S390x => clobbered_regs! {
11251155
S390x S390xInlineAsmReg {
11261156
r0, r1, r2, r3, r4, r5,

‎compiler/rustc_target/src/asm/powerpc.rs

+75-3
Original file line numberDiff line numberDiff line change
@@ -1,14 +1,17 @@
11
use std::fmt;
22

3+
use rustc_data_structures::fx::FxIndexSet;
34
use rustc_span::Symbol;
45

56
use super::{InlineAsmArch, InlineAsmType, ModifierInfo};
7+
use crate::spec::{RelocModel, Target};
68

79
def_reg_class! {
810
PowerPC PowerPCInlineAsmRegClass {
911
reg,
1012
reg_nonzero,
1113
freg,
14+
vreg,
1215
cr,
1316
xer,
1417
}
@@ -48,11 +51,44 @@ impl PowerPCInlineAsmRegClass {
4851
}
4952
}
5053
Self::freg => types! { _: F32, F64; },
54+
Self::vreg => &[],
5155
Self::cr | Self::xer => &[],
5256
}
5357
}
5458
}
5559

60+
fn reserved_r13(
61+
arch: InlineAsmArch,
62+
_reloc_model: RelocModel,
63+
_target_features: &FxIndexSet<Symbol>,
64+
target: &Target,
65+
_is_clobber: bool,
66+
) -> Result<(), &'static str> {
67+
if target.is_like_aix && arch == InlineAsmArch::PowerPC {
68+
Ok(())
69+
} else {
70+
Err("r13 is a reserved register on this target")
71+
}
72+
}
73+
74+
fn reserved_v20to31(
75+
_arch: InlineAsmArch,
76+
_reloc_model: RelocModel,
77+
_target_features: &FxIndexSet<Symbol>,
78+
target: &Target,
79+
_is_clobber: bool,
80+
) -> Result<(), &'static str> {
81+
if target.is_like_aix {
82+
match &*target.options.abi {
83+
"vec-default" => Err("v20-v31 are reserved on vec-default ABI"),
84+
"vec-extabi" => Ok(()),
85+
_ => unreachable!("unrecognized AIX ABI"),
86+
}
87+
} else {
88+
Ok(())
89+
}
90+
}
91+
5692
def_regs! {
5793
PowerPC PowerPCInlineAsmReg PowerPCInlineAsmRegClass {
5894
r0: reg = ["r0", "0"],
@@ -66,6 +102,7 @@ def_regs! {
66102
r10: reg, reg_nonzero = ["r10", "10"],
67103
r11: reg, reg_nonzero = ["r11", "11"],
68104
r12: reg, reg_nonzero = ["r12", "12"],
105+
r13: reg, reg_nonzero = ["r13", "13"] % reserved_r13,
69106
r14: reg, reg_nonzero = ["r14", "14"],
70107
r15: reg, reg_nonzero = ["r15", "15"],
71108
r16: reg, reg_nonzero = ["r16", "16"],
@@ -113,6 +150,38 @@ def_regs! {
113150
f29: freg = ["f29", "fr29"],
114151
f30: freg = ["f30", "fr30"],
115152
f31: freg = ["f31", "fr31"],
153+
v0: vreg = ["v0"],
154+
v1: vreg = ["v1"],
155+
v2: vreg = ["v2"],
156+
v3: vreg = ["v3"],
157+
v4: vreg = ["v4"],
158+
v5: vreg = ["v5"],
159+
v6: vreg = ["v6"],
160+
v7: vreg = ["v7"],
161+
v8: vreg = ["v8"],
162+
v9: vreg = ["v9"],
163+
v10: vreg = ["v10"],
164+
v11: vreg = ["v11"],
165+
v12: vreg = ["v12"],
166+
v13: vreg = ["v13"],
167+
v14: vreg = ["v14"],
168+
v15: vreg = ["v15"],
169+
v16: vreg = ["v16"],
170+
v17: vreg = ["v17"],
171+
v18: vreg = ["v18"],
172+
v19: vreg = ["v19"],
173+
v20: vreg = ["v20"] % reserved_v20to31,
174+
v21: vreg = ["v21"] % reserved_v20to31,
175+
v22: vreg = ["v22"] % reserved_v20to31,
176+
v23: vreg = ["v23"] % reserved_v20to31,
177+
v24: vreg = ["v24"] % reserved_v20to31,
178+
v25: vreg = ["v25"] % reserved_v20to31,
179+
v26: vreg = ["v26"] % reserved_v20to31,
180+
v27: vreg = ["v27"] % reserved_v20to31,
181+
v28: vreg = ["v28"] % reserved_v20to31,
182+
v29: vreg = ["v29"] % reserved_v20to31,
183+
v30: vreg = ["v30"] % reserved_v20to31,
184+
v31: vreg = ["v31"] % reserved_v20to31,
116185
cr: cr = ["cr"],
117186
cr0: cr = ["cr0"],
118187
cr1: cr = ["cr1"],
@@ -127,8 +196,6 @@ def_regs! {
127196
"the stack pointer cannot be used as an operand for inline asm",
128197
#error = ["r2", "2"] =>
129198
"r2 is a system reserved register and cannot be used as an operand for inline asm",
130-
#error = ["r13", "13"] =>
131-
"r13 is a system reserved register and cannot be used as an operand for inline asm",
132199
#error = ["r29", "29"] =>
133200
"r29 is used internally by LLVM and cannot be used as an operand for inline asm",
134201
#error = ["r30", "30"] =>
@@ -163,13 +230,17 @@ impl PowerPCInlineAsmReg {
163230
// Strip off the leading prefix.
164231
do_emit! {
165232
(r0, "0"), (r3, "3"), (r4, "4"), (r5, "5"), (r6, "6"), (r7, "7");
166-
(r8, "8"), (r9, "9"), (r10, "10"), (r11, "11"), (r12, "12"), (r14, "14"), (r15, "15");
233+
(r8, "8"), (r9, "9"), (r10, "10"), (r11, "11"), (r12, "12"), (r13, "13"), (r14, "14"), (r15, "15");
167234
(r16, "16"), (r17, "17"), (r18, "18"), (r19, "19"), (r20, "20"), (r21, "21"), (r22, "22"), (r23, "23");
168235
(r24, "24"), (r25, "25"), (r26, "26"), (r27, "27"), (r28, "28");
169236
(f0, "0"), (f1, "1"), (f2, "2"), (f3, "3"), (f4, "4"), (f5, "5"), (f6, "6"), (f7, "7");
170237
(f8, "8"), (f9, "9"), (f10, "10"), (f11, "11"), (f12, "12"), (f13, "13"), (f14, "14"), (f15, "15");
171238
(f16, "16"), (f17, "17"), (f18, "18"), (f19, "19"), (f20, "20"), (f21, "21"), (f22, "22"), (f23, "23");
172239
(f24, "24"), (f25, "25"), (f26, "26"), (f27, "27"), (f28, "28"), (f29, "29"), (f30, "30"), (f31, "31");
240+
(v0, "0"), (v1, "1"), (v2, "2"), (v3, "3"), (v4, "4"), (v5, "5"), (v6, "6"), (v7, "7");
241+
(v8, "8"), (v9, "9"), (v10, "10"), (v11, "11"), (v12, "12"), (v13, "13"), (v14, "14"), (v15, "15");
242+
(v16, "16"), (v17, "17"), (v18, "18"), (v19, "19"), (v20, "20"), (v21, "21"), (v22, "22"), (v23, "23");
243+
(v24, "24"), (v25, "25"), (v26, "26"), (v27, "27"), (v28, "28"), (v29, "29"), (v30, "30"), (v31, "31");
173244
(cr, "cr");
174245
(cr0, "0"), (cr1, "1"), (cr2, "2"), (cr3, "3"), (cr4, "4"), (cr5, "5"), (cr6, "6"), (cr7, "7");
175246
(xer, "xer");
@@ -201,5 +272,6 @@ impl PowerPCInlineAsmReg {
201272
reg_conflicts! {
202273
cr : cr0 cr1 cr2 cr3 cr4 cr5 cr6 cr7;
203274
}
275+
// f0-f31 (vsr0-vsr31) and v0-v31 (vsr32-vsr63) do not conflict.
204276
}
205277
}

‎src/doc/unstable-book/src/language-features/asm-experimental-arch.md

+16-6
Original file line numberDiff line numberDiff line change
@@ -31,9 +31,10 @@ This feature tracks `asm!` and `global_asm!` support for the following architect
3131
| NVPTX | `reg32` | None\* | `r` |
3232
| NVPTX | `reg64` | None\* | `l` |
3333
| Hexagon | `reg` | `r[0-28]` | `r` |
34-
| PowerPC | `reg` | `r[0-31]` | `r` |
35-
| PowerPC | `reg_nonzero` | `r[1-31]` | `b` |
34+
| PowerPC | `reg` | `r0`, `r[3-12]`, `r[14-28]` | `r` |
35+
| PowerPC | `reg_nonzero` | `r[3-12]`, `r[14-28]` | `b` |
3636
| PowerPC | `freg` | `f[0-31]` | `f` |
37+
| PowerPC | `vreg` | `v[0-31]` | Only clobbers |
3738
| PowerPC | `cr` | `cr[0-7]`, `cr` | Only clobbers |
3839
| PowerPC | `xer` | `xer` | Only clobbers |
3940
| wasm32 | `local` | None\* | `r` |
@@ -76,9 +77,10 @@ This feature tracks `asm!` and `global_asm!` support for the following architect
7677
| NVPTX | `reg32` | None | `i8`, `i16`, `i32`, `f32` |
7778
| NVPTX | `reg64` | None | `i8`, `i16`, `i32`, `f32`, `i64`, `f64` |
7879
| Hexagon | `reg` | None | `i8`, `i16`, `i32`, `f32` |
79-
| PowerPC | `reg` | None | `i8`, `i16`, `i32` |
80-
| PowerPC | `reg_nonzero` | None | `i8`, `i16`, `i32` |
80+
| PowerPC | `reg` | None | `i8`, `i16`, `i32`, `i64` (powerpc64 only) |
81+
| PowerPC | `reg_nonzero` | None | `i8`, `i16`, `i32`, `i64` (powerpc64 only) |
8182
| PowerPC | `freg` | None | `f32`, `f64` |
83+
| PowerPC | `vreg` | N/A | Only clobbers |
8284
| PowerPC | `cr` | N/A | Only clobbers |
8385
| PowerPC | `xer` | N/A | Only clobbers |
8486
| wasm32 | `local` | None | `i8` `i16` `i32` `i64` `f32` `f64` |
@@ -105,6 +107,10 @@ This feature tracks `asm!` and `global_asm!` support for the following architect
105107
| Hexagon | `r29` | `sp` |
106108
| Hexagon | `r30` | `fr` |
107109
| Hexagon | `r31` | `lr` |
110+
| PowerPC | `r1` | `sp` |
111+
| PowerPC | `r31` | `fp` |
112+
| PowerPC | `r[0-31]` | `[0-31]` |
113+
| PowerPC | `f[0-31]` | `fr[0-31]`|
108114
| BPF | `r[0-10]` | `w[0-10]` |
109115
| AVR | `XH` | `r27` |
110116
| AVR | `XL` | `r26` |
@@ -145,14 +151,18 @@ This feature tracks `asm!` and `global_asm!` support for the following architect
145151
| Architecture | Unsupported register | Reason |
146152
| ------------ | --------------------------------------- | ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- |
147153
| All | `sp`, `r15` (s390x) | The stack pointer must be restored to its original value at the end of an asm code block. |
148-
| All | `fr` (Hexagon), `$fp` (MIPS), `Y` (AVR), `r4` (MSP430), `a6` (M68k), `r11` (s390x), `x29` (Arm64EC) | The frame pointer cannot be used as an input or output. |
149-
| All | `r19` (Hexagon), `x19` (Arm64EC) | This is used internally by LLVM as a "base pointer" for functions with complex stack frames. |
154+
| All | `fr` (Hexagon), `fp` (PowerPC), `$fp` (MIPS), `Y` (AVR), `r4` (MSP430), `a6` (M68k), `r11` (s390x), `x29` (Arm64EC) | The frame pointer cannot be used as an input or output. |
155+
| All | `r19` (Hexagon), `r29` (PowerPC), `r30` (PowerPC), `x19` (Arm64EC) | These are used internally by LLVM as "base pointer" for functions with complex stack frames. |
150156
| MIPS | `$0` or `$zero` | This is a constant zero register which can't be modified. |
151157
| MIPS | `$1` or `$at` | Reserved for assembler. |
152158
| MIPS | `$26`/`$k0`, `$27`/`$k1` | OS-reserved registers. |
153159
| MIPS | `$28`/`$gp` | Global pointer cannot be used as inputs or outputs. |
154160
| MIPS | `$ra` | Return address cannot be used as inputs or outputs. |
155161
| Hexagon | `lr` | This is the link register which cannot be used as an input or output. |
162+
| PowerPC | `r2`, `r13` | These are system reserved registers. |
163+
| PowerPC | `lr` | The link register cannot be used as an input or output. |
164+
| PowerPC | `ctr` | The counter register cannot be used as an input or output. |
165+
| PowerPC | `vrsave` | The vrsave register cannot be used as an input or output. |
156166
| AVR | `r0`, `r1`, `r1r0` | Due to an issue in LLVM, the `r0` and `r1` registers cannot be used as inputs or outputs. If modified, they must be restored to their original values before the end of the block. |
157167
|MSP430 | `r0`, `r2`, `r3` | These are the program counter, status register, and constant generator respectively. Neither the status register nor constant generator can be written to. |
158168
| M68k | `a4`, `a5` | Used internally by LLVM for the base pointer and global base pointer. |

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