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Implement llvm.fma.v* intrinsics
cc #1405
1 parent 9a33f82 commit 48ca2d9

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2 files changed

+44
-0
lines changed

2 files changed

+44
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src/intrinsics/llvm.rs

+15
Original file line numberDiff line numberDiff line change
@@ -51,6 +51,21 @@ pub(crate) fn codegen_llvm_intrinsic_call<'tcx>(
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});
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}
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_ if intrinsic.starts_with("llvm.fma.v") => {
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intrinsic_args!(fx, args => (x,y,z); intrinsic);
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simd_trio_for_each_lane(
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fx,
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x,
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y,
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z,
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ret,
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&|fx, _lane_ty, _res_lane_ty, lane_x, lane_y, lane_z| {
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fx.bcx.ins().fma(lane_x, lane_y, lane_z)
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},
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);
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}
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_ => {
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fx.tcx
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.sess

src/intrinsics/mod.rs

+29
Original file line numberDiff line numberDiff line change
@@ -132,6 +132,35 @@ fn simd_pair_for_each_lane<'tcx>(
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}
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}
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fn simd_trio_for_each_lane<'tcx>(
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fx: &mut FunctionCx<'_, '_, 'tcx>,
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x: CValue<'tcx>,
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y: CValue<'tcx>,
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z: CValue<'tcx>,
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ret: CPlace<'tcx>,
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f: &dyn Fn(&mut FunctionCx<'_, '_, 'tcx>, Ty<'tcx>, Ty<'tcx>, Value, Value, Value) -> Value,
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) {
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assert_eq!(x.layout(), y.layout());
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let layout = x.layout();
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let (lane_count, lane_ty) = layout.ty.simd_size_and_type(fx.tcx);
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let lane_layout = fx.layout_of(lane_ty);
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let (ret_lane_count, ret_lane_ty) = ret.layout().ty.simd_size_and_type(fx.tcx);
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let ret_lane_layout = fx.layout_of(ret_lane_ty);
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assert_eq!(lane_count, ret_lane_count);
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for lane_idx in 0..lane_count {
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let x_lane = x.value_lane(fx, lane_idx).load_scalar(fx);
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let y_lane = y.value_lane(fx, lane_idx).load_scalar(fx);
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let z_lane = z.value_lane(fx, lane_idx).load_scalar(fx);
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let res_lane = f(fx, lane_layout.ty, ret_lane_layout.ty, x_lane, y_lane, z_lane);
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let res_lane = CValue::by_val(res_lane, ret_lane_layout);
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ret.place_lane(fx, lane_idx).write_cvalue(fx, res_lane);
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}
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}
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fn simd_reduce<'tcx>(
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fx: &mut FunctionCx<'_, '_, 'tcx>,
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val: CValue<'tcx>,

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