Non-ISA specifications do not add new instructions, create or change opcodes, or in any way modify the RISC-V ISA. They do help us to develop an ecosystem around the ISA Specifications.
Things you'll find here include:
If you don't find what you're looking for here, try one of our other GitHub organizations:
Documentation for the RISC-V Supervisor Binary Interface
The repo holds the draft non-ISA Server SoC specification being developed by the Server SoC specification TG and to release intermediate releases of the specification on milestones. Further downstream this repo will be used to release specifications for public review.
This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protection Unit of Input/Output devices, IOPMP for short, to regulate the accesses issued from the bus masters.
The RISC-V Server Platform specification defines a standardized set of hardware and sofware capabilities, that portable system software, such as operating systems and hypervisors, can rely on being present in a RISC-V server platform.
Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
This Fast-Track will extract the Hart-Trace Interface chapter from the E-Trace spec and turn it into a standalone spec
The RAS Error-record Register Interface provides a specification to augment RAS features in RISC-V SOC hardware to standardize reporting and logging of errors by means of a memory-mapped register interface to enable error detection, provide the facility to log the detected errors, and configuration.
