Repository navigation
Don't decode SH-4 fcnvds and fcnvsd with an odd DRn ##disasm - #27313
Merged
Merged
Conversation
fcnvds and fcnvsd only take a double register, so bit 8 of the encoding must be 0 (1111nnn0...). The table matched any nibble and printed registers that do not exist, such as dr1 and dr15. Use REG_N_D for both rows, as binutils does and as fsca already does.
1 of 3 tasks
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Description
Follow-up to #27308.
fcnvdsandfcnvsdonly take a double register, so bit 8 of the encoding is 0 (1111nnn010111101and1111nnn010101101). The table matched any nibble, sof1bdprintedfcnvds dr1, fpulandffadprintedfcnvsd fpul, dr15, registers that do not exist.Both rows now use
REG_N_D, as binutils does and as thefscarow already does. No other SH-4 instruction uses those words, so they print the usual.wordfallback.Testing
test/db/asm/sh: even registers in both byte orders, plus the odd encodings. The 4 odd-register lines fail on master.r2r db/asm: 0 failures.sys/lint.py --allis clean.