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Fix #17381 - Decode SH-4 fsca and fsrra and tighten the ftrv pattern ##disasm - #27308
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Description
Fixes #17381. The SH-4 table encoded
ftrvas{HEX_F,REG_NM,HEX_F,HEX_D}.REG_NMaccepts any nibble, so the low two bits of the register nibble, which must be01, were never checked. As a result:fsca fpul, drN(1111nnn011111101) was printed asftrv xmtrx, fvN;fsrra frN(1111nnnn01111101) had no row at all and came out as.word.Following current binutils:
REG_N_D(even register only) andREG_N_B01(low bits01);ftrvusesREG_N_B01;fscaandfsrrarows.Across all 65536 words, the only decodes that change are:
Fn7Dwords, nowfsrra;FnFDwords, nowfsca;F7FDandFFFD, now.wordinstead of a wrongftrv.F7FDis the SH-4Afpchg, which this table doesn't have.fschgandfrchgare unchanged.Note on the issue's example:
FD F1is the word0xF1FD, which is reallyftrv xmtrx, fv0(binutils and MAME agree).fscawith register 0 is0xF0FD, and its operand isdr0, notfr0.Testing
New lines in
test/db/asm/sh:fscafor dr0, dr2 and dr14, plus one little-endian line;fsrrafor fr0 and fr15;ftrvfor fv0, fv4 and fv12;fschgandfrchg, which had no tests.On master the
fscaandfsrralines fail; with this changer2r db/asm/shpasses. The fullr2r db/asmrun has 0 failures, anddb/anal/sh,db/cmd/archsanddb/cmd/cmd_phpass. Built with./configure && makeon Linux (gcc).sys/lint.py --allandgit diff --checkare clean.