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Fix #17381 - Decode SH-4 fsca and fsrra and tighten the ftrv pattern ##disasm - #27308

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trufae merged 1 commit into
radareorg:masterfrom
Thanatos9404:sh4-fsca-fsrra
Nov 2, 2026
Merged

trufae merged 1 commit into
radareorg:masterfrom
Thanatos9404:sh4-fsca-fsrra

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Description

Fixes #17381. The SH-4 table encoded ftrv as {HEX_F,REG_NM,HEX_F,HEX_D}. REG_NM accepts any nibble, so the low two bits of the register nibble, which must be 01, were never checked. As a result:

  • fsca fpul, drN (1111nnn011111101) was printed as ftrv xmtrx, fvN;
  • fsrra frN (1111nnnn01111101) had no row at all and came out as .word.

Following current binutils:

  • the matcher gets two nibble types, REG_N_D (even register only) and REG_N_B01 (low bits 01);
  • ftrv uses REG_N_B01;
  • the table gains the fsca and fsrra rows.

Across all 65536 words, the only decodes that change are:

  • the 16 Fn7D words, now fsrra;
  • the 8 even FnFD words, now fsca;
  • F7FD and FFFD, now .word instead of a wrong ftrv. F7FD is the SH-4A fpchg, which this table doesn't have.

fschg and frchg are unchanged.

Note on the issue's example: FD F1 is the word 0xF1FD, which is really ftrv xmtrx, fv0 (binutils and MAME agree). fsca with register 0 is 0xF0FD, and its operand is dr0, not fr0.

Testing

New lines in test/db/asm/sh:

  • fsca for dr0, dr2 and dr14, plus one little-endian line;
  • fsrra for fr0 and fr15;
  • ftrv for fv0, fv4 and fv12;
  • fschg and frchg, which had no tests.

On master the fsca and fsrra lines fail; with this change r2r db/asm/sh passes. The full r2r db/asm run has 0 failures, and db/anal/sh, db/cmd/archs and db/cmd/cmd_ph pass. Built with ./configure && make on Linux (gcc). sys/lint.py --all and git diff --check are clean.

@trufae
trufae merged commit 2f7edc8 into radareorg:master Nov 2, 2026
44 of 45 checks passed
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SH-4 instruction set: undocumented FSCA / FSRRA instruction being incorrectly read as FTRV

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