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Fix i/o addresses and pre-decrement pointers in the AVR assembler ##arch - #27135
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trufae
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- The
-x/-y/-zfix looks good. The post-increment forms still work. - Please check the full I/O number before narrowing it.
out 0x100000001, r1currently becomesout 1, r1.sbi 0x10000000c, 5becomessbi 12, 5. - Please reject trailing junk too.
out 1junk, r1is accepted.out 0x, r1silently writes to address zero. The inline suggestion covers both parsing issues. - Add rejection tests for those four cases and an integer overflow such as
out 18446744073709551616, r1. Also coverout 63/64andsbi 31/32, with valid bit/register operands. - Keep tests for
spl,sphandsreg. They should still work without. They must be rejected by the 5-bit I/O instructions. - One existing gap:
inusesOPERAND_DATA, so the new check skips it.in r1, 64still encodes address zero. This is not a regression and can be a separate follow-up. Either change that operand toOPERAND_IO_REGISTERand add boundary tests, or adjust the helper comment so it doesn't claim to coverin.
I checked 6,720 valid I/O and pointer encodings in a focused harness using this assembler. Those passed. The small parser suggestion was also checked against the bad inputs and the normal limits.
… assembler ##arch
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done in 7be738f . took your suggestion as is , so the whole token is read as a 64 bit value and anything with junk after it or above 0x3f is rejected before
tests : the first commit was only reworded , its diff is the same . |
Description
two things in the AVR assembler produced a different instruction without an error :
out 1, r1out 0, r111b8sbi 12, 5sbi 0, 5659ald r10, -Zld r10, Z+a290st -X, r11st X+, r11be92assemble_general_io_operandonly knowsspl,sphandsreg( and their addresses ) , the numeric branch was commented out , andassemble_operandreturned success anyway , so every other i/o address inout,sbi,cbi,sbicandsbisbecame 0 . numbers are taken again , and checked against the width of the field , 6 bits foroutand 5 for the bit instructions , soout 64, r5andsbi 32, 0are refused instead of wrappingRegsTablemapped-x,-yand-ztoOPERAND_XP,OPERAND_YPandOPERAND_ZP, the post-increment forms , the pre-decrement onesOPERAND_MX,OPERAND_MYandOPERAND_MZwere already in the instruction tablefound by decoding random words with llvm-mc (
-mcpu=avr6) , assembling the text withrasm2 -a avrand decoding the result again . same as llvm went from 4333 to 4606 of 5470 , nothing that was right changed . what is left isrjmp .+Nstyle relative operands , where rasm2 takes an address instead . the 11 new lines indb/asm/avrfail before the change ,db/asmanddb/tools/rasm2have no failures .