Fix stores, srai and jalr in the RISC-V assembler ##arch - #27133

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Description

the RISC-V assembler sent everything through the I-type encoder , so some instructions came out as something else :

• stores use the S-type layout , and sb , sh and sd are added next to sw
• srai has its 0x20 funct7 , slli and srli are added , the shift amount is checked to be 0..63
• jalr and jr take rs , rd, rs , imm(rs) and rd, imm(rs)
• the loads lb , lh , ld , lbu , lhu and lwu are added , they work like lw
• I and S immediates outside -2048..2047 , or a missing register , are refused instead of being or'ed into other fields

found by decoding random words with llvm-mc , assembling the text with rasm2 -a riscv and decoding the result again . out of 3482 distinct instructions , 880 came back the same before and 1934 now , the wrong ones went from 315 to 5 ( c.nop with a hint immediate ) and none that were right changed . the 16 new lines in db/asm/riscv_64 check against llvm's bytes , 15 of them fail before the change . db/asm has no failures .