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Deselect ruff-covered pylint rules (#7424)
And clean up associated pylint directives in the code. No change in the effective code. Partially implements #7371
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‎CONTRIBUTING.md‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -137,8 +137,8 @@ constructs. We use [Pylint](https://www.pylint.org/) to check for code lint.
137137
To see which lint checks we enforce, see the
138138
[dev_tools/conf/.pylintrc](dev_tools/conf/.pylintrc) file. When Pylint produces
139139
a false positive, it can be silenced with annotations. For example, the
140-
annotation `# pylint: disable=unused-import` would silence a warning about
141-
an unused import.
140+
annotation `# pylint: disable=wrong-import-order` would silence a warning about
141+
wrong import order.
142142
143143
### Types
144144

‎cirq-core/cirq/__init__.py‎

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -123,7 +123,6 @@
123123
)
124124

125125
from cirq.linalg import (
126-
# pylint: disable=line-too-long
127126
all_near_zero as all_near_zero,
128127
all_near_zero_mod as all_near_zero_mod,
129128
allclose_up_to_global_phase as allclose_up_to_global_phase,
@@ -344,7 +343,6 @@
344343

345344

346345
from cirq.transformers import (
347-
# pylint: disable=line-too-long
348346
AbstractInitialMapper as AbstractInitialMapper,
349347
add_dynamical_decoupling as add_dynamical_decoupling,
350348
align_left as align_left,
@@ -572,7 +570,6 @@
572570
ProductState as ProductState,
573571
)
574572

575-
# pylint: disable=redefined-builtin
576573
from cirq.protocols import (
577574
act_on as act_on,
578575
apply_channel as apply_channel,
@@ -694,12 +691,10 @@
694691
ZerosSampler as ZerosSampler,
695692
)
696693

697-
# pylint: enable=redefined-builtin
698694

699695
# Unflattened sub-modules.
700696

701697
# Registers cirq-core's public classes for JSON serialization.
702-
# pylint: disable=wrong-import-position
703698
from cirq.protocols.json_serialization import _register_resolver
704699
from cirq.json_resolver_cache import _class_resolver_dictionary
705700

@@ -709,5 +704,3 @@
709704
# contrib's json resolver cache depends on cirq.DEFAULT_RESOLVER
710705

711706
from cirq import contrib # noqa: E402
712-
713-
# pylint: enable=wrong-import-position

‎cirq-core/cirq/_compat_test.py‎

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -394,13 +394,11 @@ class OldClass(NewClass):
394394
OldClass('1')
395395

396396
with pytest.raises(AssertionError, match='deadline should match vX.Y'):
397-
# pylint: disable=unused-variable
397+
398398
@deprecated_class(deadline='invalid', fix='theFix', name='foo')
399399
class BadlyDeprecatedClass(NewClass): # pragma: no cover
400400
...
401401

402-
# pylint: enable=unused-variable
403-
404402

405403
def _from_parent_import_deprecated():
406404
from cirq.testing._compat_test_data import fake_a
@@ -566,7 +564,6 @@ def _import_top_level_deprecated():
566564
def _repeated_import_path():
567565
"""to ensure that the highly unlikely repeated subpath import doesn't interfere"""
568566

569-
# pylint: disable=line-too-long
570567
from cirq.testing._compat_test_data.repeated_child.cirq.testing._compat_test_data.repeated_child import ( # type: ignore # noqa: E501
571568
child,
572569
)
@@ -812,7 +809,6 @@ def _test_broken_module_1_inner():
812809
with pytest.raises(
813810
DeprecatedModuleImportError, match="missing_module cannot be imported. The typical reasons"
814811
):
815-
# pylint: disable=unused-import
816812
import cirq.testing._compat_test_data.broken_ref as br # type: ignore # noqa: F401
817813

818814

‎cirq-core/cirq/contrib/paulistring/clifford_target_gateset.py‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -79,7 +79,7 @@ class SingleQubitTarget(Enum):
7979
def __init__(
8080
self,
8181
*,
82-
single_qubit_target: SingleQubitTarget = SingleQubitTarget.PAULI_STRING_PHASORS_AND_CLIFFORDS, # pylint: disable=line-too-long # noqa: E501
82+
single_qubit_target: SingleQubitTarget = SingleQubitTarget.PAULI_STRING_PHASORS_AND_CLIFFORDS, # noqa: E501
8383
atol: float = 1e-8,
8484
):
8585
"""Initializes CliffordTargetGateset

‎cirq-core/cirq/experiments/__init__.py‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,6 @@
3737
)
3838

3939
from cirq.experiments.random_quantum_circuit_generation import (
40-
# pylint: disable=line-too-long
4140
GRID_ALIGNED_PATTERN as GRID_ALIGNED_PATTERN,
4241
GRID_STAGGERED_PATTERN as GRID_STAGGERED_PATTERN,
4342
HALF_GRID_STAGGERED_PATTERN as HALF_GRID_STAGGERED_PATTERN,

‎cirq-core/cirq/json_resolver_cache.py‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -237,9 +237,7 @@ def _symmetricalqidpair(qids):
237237
'VirtualTag': cirq.VirtualTag,
238238
'WaitGate': cirq.WaitGate,
239239
# The formatter keeps putting this back
240-
# pylint: disable=line-too-long
241240
'XEBPhasedFSimCharacterizationOptions': cirq.experiments.XEBPhasedFSimCharacterizationOptions, # noqa: E501
242-
# pylint: enable=line-too-long
243241
'_XEigenState': cirq.value.product_state._XEigenState,
244242
'XPowGate': cirq.XPowGate,
245243
'XXPowGate': cirq.XXPowGate,

‎cirq-core/cirq/linalg/__init__.py‎

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Original file line numberDiff line numberDiff line change
@@ -26,7 +26,6 @@
2626
)
2727

2828
from cirq.linalg.decompositions import (
29-
# pylint: disable=line-too-long
3029
axis_angle as axis_angle,
3130
AxisAngleDecomposition as AxisAngleDecomposition,
3231
deconstruct_single_qubit_matrix_into_angles as deconstruct_single_qubit_matrix_into_angles,
@@ -44,7 +43,6 @@
4443
)
4544

4645
from cirq.linalg.diagonalize import (
47-
# pylint: disable=line-too-long
4846
bidiagonalize_real_matrix_pair_with_symmetric_products as bidiagonalize_real_matrix_pair_with_symmetric_products, # noqa: E501
4947
bidiagonalize_unitary_with_special_orthogonals as bidiagonalize_unitary_with_special_orthogonals, # noqa: E501
5048
diagonalize_real_symmetric_and_sorted_diagonal_matrices as diagonalize_real_symmetric_and_sorted_diagonal_matrices, # noqa: E501

‎cirq-core/cirq/ops/classically_controlled_operation_test.py‎

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -505,7 +505,6 @@ def test_scope_local() -> None:
505505
assert internal_control_keys == ['0:0:a', '0:1:a', '1:0:a', '1:1:a']
506506
assert not cirq.control_keys(outer_subcircuit)
507507
assert not cirq.control_keys(circuit)
508-
# pylint: disable=line-too-long
509508
cirq.testing.assert_has_diagram(
510509
cirq.Circuit(outer_subcircuit),
511510
"""
@@ -515,7 +514,6 @@ def test_scope_local() -> None:
515514
""", # noqa: E501
516515
use_unicode_characters=True,
517516
)
518-
# pylint: enable=line-too-long
519517
cirq.testing.assert_has_diagram(
520518
circuit,
521519
"""
@@ -659,7 +657,6 @@ def test_scope_extern() -> None:
659657
assert internal_control_keys == ['0:b', '0:b', '1:b', '1:b']
660658
assert not cirq.control_keys(outer_subcircuit)
661659
assert not cirq.control_keys(circuit)
662-
# pylint: disable=line-too-long
663660
cirq.testing.assert_has_diagram(
664661
cirq.Circuit(outer_subcircuit),
665662
"""
@@ -671,7 +668,6 @@ def test_scope_extern() -> None:
671668
""", # noqa: E501
672669
use_unicode_characters=True,
673670
)
674-
# pylint: enable=line-too-long
675671
cirq.testing.assert_has_diagram(
676672
circuit,
677673
"""
@@ -780,7 +776,6 @@ def test_scope_extern_mismatch() -> None:
780776
assert internal_control_keys == ['b', 'b', 'b', 'b']
781777
assert cirq.control_keys(outer_subcircuit) == {cirq.MeasurementKey('b')}
782778
assert cirq.control_keys(circuit) == {cirq.MeasurementKey('b')}
783-
# pylint: disable=line-too-long
784779
cirq.testing.assert_has_diagram(
785780
cirq.Circuit(outer_subcircuit),
786781
"""
@@ -794,7 +789,6 @@ def test_scope_extern_mismatch() -> None:
794789
""", # noqa: E501
795790
use_unicode_characters=True,
796791
)
797-
# pylint: enable=line-too-long
798792
cirq.testing.assert_has_diagram(
799793
circuit,
800794
"""
@@ -984,7 +978,6 @@ def test_sympy_scope() -> None:
984978
use_unicode_characters=True,
985979
)
986980

987-
# pylint: disable=line-too-long
988981
cirq.testing.assert_has_diagram(
989982
circuit,
990983
"""
@@ -1000,7 +993,6 @@ def test_sympy_scope() -> None:
1000993
""", # noqa: E501
1001994
use_unicode_characters=True,
1002995
)
1003-
# pylint: enable=line-too-long
1004996

1005997

1006998
def test_sympy_scope_simulation() -> None:

‎cirq-core/cirq/ops/clifford_gate_test.py‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -125,7 +125,6 @@ def test_init_from_double_invalid(trans1, from1) -> None:
125125
@pytest.mark.parametrize('trans,frm', itertools.product(_all_rotations(), _paulis))
126126
def test_init_from_single_map_vs_kwargs(trans, frm) -> None:
127127
from_str = str(frm).lower() + '_to'
128-
# pylint: disable=unexpected-keyword-arg
129128
gate_kw = cirq.SingleQubitCliffordGate.from_single_map(**{from_str: trans})
130129
gate_map = cirq.SingleQubitCliffordGate.from_single_map({frm: trans})
131130
assert gate_kw == gate_map

‎cirq-core/cirq/ops/fsim_gate_test.py‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -490,7 +490,6 @@ def test_phased_fsim_circuit() -> None:
490490
1: ───PhFSim(0.5π, -π, 0.5π, 0, -0.25π)───PhFSim(-π, 0.5π, 0.1π, 0.2π, 0.3π)───
491491
""",
492492
)
493-
# pylint: disable=line-too-long
494493
cirq.testing.assert_has_diagram(
495494
c,
496495
"""
@@ -510,7 +509,6 @@ def test_phased_fsim_circuit() -> None:
510509
use_unicode_characters=False,
511510
precision=None,
512511
)
513-
# pylint: enable=line-too-long
514512
c = cirq.Circuit(
515513
cirq.PhasedFSimGate(
516514
sympy.Symbol('a') + sympy.Symbol('b'),

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