Make CUDA triu / tril support batches of size > 65535 #21067
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I'm ok with this PR if we need only functional support, if performance is important some changes are necessary. Code is nicely simplified.
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@ngimel This is not a necessarily performance critical kernel - it's generally used in tandem with many linear algebra operations. However, since you mentioned that indexing based on int32 helps a lot for smaller inputs, I've incorporated it in the PR. |
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@pytorchbot rebase this please |
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@pytorchbot merge this please |
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@ezyang is landing this pull request. If you are a Facebook employee, you can view this diff on Phabricator.
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Summary: In the previous implementation of triu / tril, we passed the batch size in the 2nd dimension of a grid. This is limited to 65535, which means that performing triu / tril on a tensor with batch size > 65535 will throw an error. This PR removes the dependence on the 2nd dimension, and corresponding non-contiguity constraints. Changelog: - Compute offset, row and col in the kernel - Use 1st dimension of grid alone - Remove unnecessary contiguity checks on tensors as a result of this change. Pull Request resolved: pytorch/pytorch#21067 Differential Revision: D15572501 Pulled By: ezyang fbshipit-source-id: 93851cb661918ce794d43eeb12c8a38762e1358c
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In the previous implementation of triu / tril, we passed the batch size in the 2nd dimension of a grid. This is limited to 65535, which means that performing triu / tril on a tensor with batch size > 65535 will throw an error. This PR removes the dependence on the 2nd dimension, and corresponding non-contiguity constraints.
Changelog:
Test Plan: