Improve the CPUINFO display for RISC-V#28760
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bernd-edlinger wants to merge 2 commits intoopenssl:masterfrom
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Improve the CPUINFO display for RISC-V#28760bernd-edlinger wants to merge 2 commits intoopenssl:masterfrom
bernd-edlinger wants to merge 2 commits intoopenssl:masterfrom
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Prefix the base architecture to the displayed RISC-V architecture string, so the displayed OPENSSL_riscvcap environment value can be used as is, since otherwise the OPENSSL_cpuid_setup would ignore the first extension, as it is expected to be the base architecture, usually "RV64GC" or similar. See the comment at parse_env in crypto/riscvcap.c Furthermore also print the VLEN value, if the V-extension is given, since that makes a significant difference which assembler modules are activated by the V-extension.
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This PR is in a state where it requires action by @openssl/committers but the last update was 30 days ago |
paulidale
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Nov 7, 2025
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This pull request is ready to merge |
openssl-machine
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Nov 10, 2025
Reviewed-by: Paul Dale <[email protected]> Reviewed-by: Dmitry Belyavskiy <[email protected]> (Merged from #28760) (cherry picked from commit 70b3250)
openssl-machine
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Nov 10, 2025
Prefix the base architecture to the displayed RISC-V architecture string, so the displayed OPENSSL_riscvcap environment value can be used as is, since otherwise the OPENSSL_cpuid_setup would ignore the first extension, as it is expected to be the base architecture, usually "RV64GC" or similar. See the comment at parse_env in crypto/riscvcap.c Furthermore also print the VLEN value, if the V-extension is given, since that makes a significant difference which assembler modules are activated by the V-extension. Reviewed-by: Paul Dale <[email protected]> Reviewed-by: Dmitry Belyavskiy <[email protected]> (Merged from #28760) (cherry picked from commit c05ea2f)
openssl-machine
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that referenced
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Nov 10, 2025
Reviewed-by: Paul Dale <[email protected]> Reviewed-by: Dmitry Belyavskiy <[email protected]> (Merged from #28760) (cherry picked from commit 70b3250)
openssl-machine
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Nov 10, 2025
Prefix the base architecture to the displayed RISC-V architecture string, so the displayed OPENSSL_riscvcap environment value can be used as is, since otherwise the OPENSSL_cpuid_setup would ignore the first extension, as it is expected to be the base architecture, usually "RV64GC" or similar. See the comment at parse_env in crypto/riscvcap.c Furthermore also print the VLEN value, if the V-extension is given, since that makes a significant difference which assembler modules are activated by the V-extension. Reviewed-by: Paul Dale <[email protected]> Reviewed-by: Dmitry Belyavskiy <[email protected]> (Merged from #28760) (cherry picked from commit c05ea2f)
openssl-machine
pushed a commit
that referenced
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Nov 10, 2025
Reviewed-by: Paul Dale <[email protected]> Reviewed-by: Dmitry Belyavskiy <[email protected]> (Merged from #28760) (cherry picked from commit 70b3250)
openssl-machine
pushed a commit
that referenced
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Nov 10, 2025
Prefix the base architecture to the displayed RISC-V architecture string, so the displayed OPENSSL_riscvcap environment value can be used as is, since otherwise the OPENSSL_cpuid_setup would ignore the first extension, as it is expected to be the base architecture, usually "RV64GC" or similar. See the comment at parse_env in crypto/riscvcap.c Furthermore also print the VLEN value, if the V-extension is given, since that makes a significant difference which assembler modules are activated by the V-extension. Reviewed-by: Paul Dale <[email protected]> Reviewed-by: Dmitry Belyavskiy <[email protected]> (Merged from #28760) (cherry picked from commit c05ea2f)
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Merged to all branches. Thanks! |
openssl-machine
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Nov 10, 2025
Reviewed-by: Paul Dale <[email protected]> Reviewed-by: Dmitry Belyavskiy <[email protected]> (Merged from #28760)
openssl-machine
pushed a commit
that referenced
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Nov 10, 2025
Prefix the base architecture to the displayed RISC-V architecture string, so the displayed OPENSSL_riscvcap environment value can be used as is, since otherwise the OPENSSL_cpuid_setup would ignore the first extension, as it is expected to be the base architecture, usually "RV64GC" or similar. See the comment at parse_env in crypto/riscvcap.c Furthermore also print the VLEN value, if the V-extension is given, since that makes a significant difference which assembler modules are activated by the V-extension. Reviewed-by: Paul Dale <[email protected]> Reviewed-by: Dmitry Belyavskiy <[email protected]> (Merged from #28760)
MegaManSec
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Nov 11, 2025
Reviewed-by: Paul Dale <[email protected]> Reviewed-by: Dmitry Belyavskiy <[email protected]> (Merged from openssl#28760)
MegaManSec
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Prefix the base architecture to the displayed RISC-V architecture string, so the displayed OPENSSL_riscvcap environment value can be used as is, since otherwise the OPENSSL_cpuid_setup would ignore the first extension, as it is expected to be the base architecture, usually "RV64GC" or similar. See the comment at parse_env in crypto/riscvcap.c Furthermore also print the VLEN value, if the V-extension is given, since that makes a significant difference which assembler modules are activated by the V-extension. Reviewed-by: Paul Dale <[email protected]> Reviewed-by: Dmitry Belyavskiy <[email protected]> (Merged from openssl#28760)
openssl-machine
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Jan 27, 2026
3.6.1 CHANGES.md includes the following: * #28760 "Improve the CPUINFO display for RISC-V" * #28797 "Fix regression when X509_V_FLAG_CRL_CHECK_ALL is set" * #28955 "Fix for TLS handshake issue with GnuTLS #28902" * #29155 "fix(x509.c): fixed -checkend return values" * #29214 "s390x: Check and fail on invalid malformed ECDSA signatures" * #29245 "Clang format 3.6" * #29251 "Fix change of behavior of the single stapled OCSP response API" 3.6.1 NEWS.md includes the following: * #28797 "Fix regression when X509_V_FLAG_CRL_CHECK_ALL is set" * #28955 "Fix for TLS handshake issue with GnuTLS #28902" Co-Authored-by: Tomáš Mráz <[email protected]> Signed-off-by: Eugene Syromiatnikov <[email protected]> Reviewed-by: Nikola Pajkovsky <[email protected]> Reviewed-by: Neil Horman <[email protected]> Reviewed-by: Saša Nedvědický <[email protected]> Reviewed-by: Tomas Mraz <[email protected]> MergeDate: Mon Jan 26 20:01:30 2026
openssl-machine
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Jan 27, 2026
3.5.5 CHANGES.md includes the following: * #28760 "Improve the CPUINFO display for RISC-V" * #29214 "s390x: Check and fail on invalid malformed ECDSA signatures" * #29262 "Clang format 3.5" Co-Authored-by: Tomáš Mráz <[email protected]> Signed-off-by: Eugene Syromiatnikov <[email protected]> Reviewed-by: Saša Nedvědický <[email protected]> Reviewed-by: Neil Horman <[email protected]> Reviewed-by: Tomas Mraz <[email protected]> MergeDate: Mon Jan 26 20:03:05 2026
openssl-machine
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Jan 27, 2026
3.4.4 CHANGES.md includes the following: * #28760 "Improve the CPUINFO display for RISC-V" * #29214 "s390x: Check and fail on invalid malformed ECDSA signatures" * #29260 "Clang format 3.4" Co-Authored-by: Tomáš Mráz <[email protected]> Signed-off-by: Eugene Syromiatnikov <[email protected]> Reviewed-by: Saša Nedvědický <[email protected]> Reviewed-by: Neil Horman <[email protected]> Reviewed-by: Tomas Mraz <[email protected]> MergeDate: Mon Jan 26 20:04:13 2026
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Prefix the base architecture to the displayed RISC-V
architecture string, so the displayed OPENSSL_riscvcap
environment value can be used as is, since otherwise
the OPENSSL_cpuid_setup would ignore the first extension,
as it is expected to be the base architecture, usually
"RV64GC" or similar.
See the comment at parse_env in crypto/riscvcap.c
Furthermore also print the VLEN value, if the V-extension
is given, since that makes a significant difference
which assembler modules are activated by the V-extension.
Checklist