Repository navigation
RISC-V SM2 implementation CI regression #28731
Description
RISC-V SM2 implementation does not work correctly anymore with dff94db applied.
That fix was added to avoid timing side channel in the modular inversion on ARM.
After that fix was applied to the master branch the RISC-V CI jobs fail:
https://github.com/openssl/openssl/actions/runs/18187228212/job/51774044227
# INFO: @ test/ec_internal_test.c:226
# Testing curve brainpoolP512t1
#
# INFO: @ test/ec_internal_test.c:226
# Testing curve SM2
#
# ERROR: (bool) 'BN_is_one(b) == true' failed @ test/ec_internal_test.c:40
# false
# ok 81 - iteration 81
# # OPENSSL_TEST_RAND_SEED=1759392980
# not ok 82 - iteration 82
# # OPENSSL_TEST_RAND_SEED=1759392980
# not ok 5 - field_tests_default
Activity
t8m commentedon Oct 2, 2025
@geliyaz Could you please look at this as the author of the RISC-V SM2 implementation?
t8m commentedon Oct 3, 2025
If we do not get a fix soon, we will have to revert #25918 unfortunately.
Fix riscv64 carry bug in SM2 modulo reduction
Fix riscv64 carry bug in SM2 modulo reduction