Pinned Loading

1. 5-Stage-RISC-V-CPU 5-Stage-RISC-V-CPU Public

   A 5 stage risc-v cpu built in verilog. The CPU is pipelined to contain 5 stages (F, D, X, M, W). Hazard handling has also been implemented (RAW) and flushing and stall logic. CPU confirmed using al…

   VHDL

2. iBERT-LLM iBERT-LLM Public

   The BERT LLM modified to be accelerated on hardware using an integer approximation of the model, hence iBERT. Modules such as divide, exponent, softmax, and layernorm were modified to be integer ve…

   SystemVerilog