Commits

• dd0e2eb: Fix operator precedence in assembler expression evaluation (#490) (Hardik Garg) #490

Bug fixes

• Fixed the Light/Dark color scheme setting having no effect in the Linux AppImage (#480). Ripes is now built with Qt 6.10.3.
• Fixed the GetCWD ecall writing the whole path to a single byte and not null-terminating it (#478).

New features

• Qt 6: Ripes has been migrated to Qt 6, and the macOS release is now a universal (Apple Silicon + Intel) build.
• Ripes in the browser: a WebAssembly build of Ripes is available at ripes.dk.
• New processor models:
  • A 5-stage multicycle processor (with one or two memories), based on the work of Francisco Valero Gil.
  • An ISA simulator "processor" model (RV32_ISS/RV64_ISS) for fast, non-pipelined execution.
• Theming: Light/Dark/System color schemes with live theme switching.
• New memory-mapped I/O peripherals: a raster screen, a real-time clock, and an edge-capture/latching D-pad.
• Command line mode:
  • ELF and C files can now be executed from the CLI.
  • System input (stdin) handling for CLI execution.
  • Cache simulation is now available in the CLI (--cache-preset).
• Assembler:
  • GNU-style offset(base) memory operands (e.g. lw t0, 4(sp), lw t0, (sp), jalr ra, 4(t0), c.lw a0, 4(a1), c.lwsp a0, 4(sp)).
  • Labels may now start with a dot.
• Caches: non-power-of-two associativities are now supported, and cache configuration now uses the term "sets" instead of "lines".
• UI:
  • Added a memory viewer widget to the edit and processor tabs; register values can be copied from the register widget and followed into memory (right click).
  • Panning in the cache graphic view, a modernized sidebar, and persisted window geometry.
  • Added a setting for enabling VSRTL VCD tracing.

Bug fixes

• Processor models:
  • jalr did not clear the least significant bit of the target address (#477).
  • Register shift instructions (sll/srl/sra) used all bits of rs2 instead of only the lower 5 (RV32) or 6 (RV64) bits (#398).
  • Incorrect mulh/mulhu/mulhsu results on 64-bit processors.
  • Compressed c.j/c.jal instructions jumping to the wrong address for offsets below -1024 (#472).
  • Incorrect EX stage stall in the 5-stage pipeline (#444).
  • Fixed RVC prime register encoding/decoding.
• Assembler:
  • c.j/c.jal/c.beqz/c.bnez encoded label targets as absolute rather than PC-relative addresses (#411).
  • sw rs2, SYMBOL(rs1) with a symbolic offset was assembled as the sw rs2, label, rt pseudo-instruction (#467).
  • Superfluous instruction operands are now rejected rather than silently ignored.
  • Disabled ISA extensions of a processor were still accepted by the assembler.
  • Hex/binary representations of edge-case signed immediates (e.g. 0xFFFFFFFF) are now accepted.
  • Division by zero in constant expressions crashed the assembler (#347).
  • Parentheses were matched before comments were removed (#421).
• Caches: fixed the random replacement policy, ensured a minimum of one way, and fixed numeric limits for way counts and presets.
• System calls: fixed the read syscall character count being halved, the O_CREAT flag in open, read-only file operations, and added a stack-heap collision check to brk.
• UI and misc:
  • Auto-clocking was not stopped when a breakpoint was hit.
  • A breakpoint at line 0 was also mirrored at line num instructions.
  • I/O devices are now updated upon processor reset.
  • Fixed a crash when hovering over the cache statistics chart.
  • Fixed memory leaks in I/O simulation.
  • Console input and clipboard usage in the WebAssembly build (#304).
  • Source code highlighting with programs loaded at a non-zero start address.

Ripes v2.2.6

Bug fixes and minor stuff

• Fixed crash when changing processor layout due to incorrect processor label IDs.
• Changed the terminology for caches, substituting "Word" for "Block". Most textbooks use the term "cache block" interchangeably with "cache line", so using "Block" for words stored in a cache line was confusing.

Ripes v2.2.5

New Features:

• Ripes command line mode
  • Ripes can now be executed without the GUI to support batch and headless execution, as well as to integrate into other flows.
  • An example run is: ./Ripes --mode sh --src complexMul.s -t asm --proc "RV32_6S_DUAL" --isaexts M,C --cpi --cycles --pipeline
  • See ./Ripes --help for the full list of supported telemetry and options.

Bug fixes and minor stuff

• Added new example for reading from STDIN in assembly
• Fixed deadlock when resetting processor while waiting for user input
• Fixed zombie state when exiting the application while "running" the processor
• Fixed string literal tokenizer; '\"' and ':' are now allowed inside string directives.
• Added register column to system call help window.
• Added support for local/relative labels in assembler.
• Fixed pipeline diagram not updating

Ripes V2.2.4

New features:

• Support for the RISC-V compressed instruction set for all processors (big thanks to @lcgamboa for taking care of the processor model implementation!).
• Support for clang-format'ting .c files
• Added source code stage highlighting. Enabled for C code when programs are compiled with -g.
  Note: If you've used Ripes prior to this version, you must manually add -g to "compiler arguments in settings->compiler->compiler arguments. For new users, -g will be added by default.

Bug fixes:

• Fixed race condition when autoclocking the single cycle processor which allowed for executing instructions beyond an ecall exit instruction
• Fixed issue in verifying ELF flags, which could sometimes lead to compiler autodetection failing
• Fixed issue in reloading integer settings values which represented unsigned integers
• A bunch of small fixes to issues relating to persisting save file path information.
• Fixed issue in loading flat binary files containing 0x0D (CR) characters.
• Fix issue where parent directories were not being created when saving files.

Ripes V2.2.3

Bug fixes:

• Memory viewer showing incorrect values for 64-bit processors
• Fix some 32-bit hardcoding in cache sim and cache viz
• ProcessorHandler futurewatcher signals were reconnected on each invocation of run, essentially creating a linear increase in execution time after each run invokation which slowed down the application over time.

Ripes v2.2.2

New features/changes:

• 64 bit support (RV64IM) for all current processors. This implies support for RV64IM instructions in the built-in assembler as well as compiler support for RV64 compatible baremetal toolchains
• Added a register view in the edit tab (may be disabled in settings)
• The current processor and ISA are now shown in the status bar
• Added %hi and %lo relocations
• Cache plot marker values are now shown in cache legend
• Various quality of life changes in the editor (indentation, parenthesis completion, ...)

Bug fixes:

• Stage information was not always being update in the program viewer (only an issue with the 6 stage model).
• The symbol navigator was using incorrect symbol addresses. This was only a real issue on large, compiled programs.
• Fixed layering issues with port value labels
• Fix crashes on startup and shutdown on macOS
• Fixed cache graphic not updating after run finished
• Fixed possible crash when changing cache preset during stepping the processor