Digital hardware design and embedded AI hardware systems
Highlights
- Pro
Pinned Loading
-
sobel-edge-detection-fpga
sobel-edge-detection-fpga PublicA convolution-based Sobel edge detection system on the Nexys A7 FPGA.
Verilog 1
-
-
gate-level-alu
gate-level-alu PublicA 4-bit Arithmetic Logic Unit (ALU) built at gate level abstraction and implemented on the Basys 3 Artix-7 FPGA.
Verilog 1
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.