-
-
Notifications
You must be signed in to change notification settings - Fork 8.6k
STM32G4: add support for G4 series, and LPUART #6911
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Conversation
|
I now have some STM32G4 hardware so can test this. |
|
Ah, great, I have the Nucleo board that's included in the boards folder (G474RE), and tested it quite well. The only thing I missed was LPUART support (now included in this version, but I don't have other Nucleo boards to test if they all work). Sorry for still adding stuff, I seem to have some troubles with the ci scripts (I suddely have/had a pull_request branch?). I fixed the pyb issue, but due to STM32lib switched to vendor (I integrated it into vendor, as it is based on the vendor version) the build now fails on some unfixed bugs in the vendor tree. I also tried to build for the G431 board, but the Flash space was not sufficient. So I didn't include the files for that board. |
|
If you need some help with integrating into the right branches etc, please leave a note and I will try to help. |
|
The stm32lib repository has now been updated to include the G4 HAL, on the branch: |
chrismas9
left a comment
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
ports/stm32/boards/stm32g474.ld
I think the fs cache is overlapping the heap and file writes will crash the middle of the heap (if used). CCMRAM at 0x10000000 is also mapped after SRAM1 and SRAM2 and is the last part of the continuous 128KB at 0x20000000. There is only 128KB ram total comprising SRAM1 (80KB), SRAM2 (16KB) and CCMRAM (32KB).
The best layout for devices with continuous RAM is to not define RAM at 0x10000000 and just use one block at 0x20000000. Have a look at the STM32L496 linker script. Layout would be 4k fs_cache at top, then stack, then heap.
Also for devices with uniform flash sector size there is no need for FLASH_ISR. It's only needed for the F4 & F7 series to take advantage of the small sectors at the start of flash. Again look at the L496 for simpler config with FLASH first, then FLASH_FS.
|
Sorry for the delay, had some other priorities, I'll pick it up today. I've changed the setup for the G4 as @chrismas9 suggested, and the build still work on the Nucleo board. Now running the ci tests to see if it all builds. |
|
I've updated with the comments or @chrismas9 and did some more testing (I2C, SPI, UART, Switch, LED, Timer). Found a bug in my code for timer1 callback, but also for general callback (also tested on WB series). You can't register a callback when the timer is running. Stopping before starting the timer in the callback registering function fixes this. I do get errors when using the deploy-stlink after building. But that seems to be an issue with st-flash. If I execute a mass-erase with st-flash, the deploy is working, but that also means custom py scripts are erased. Normally, I think, using the reset and user button, in mode 3, the filesystem is renewed but somehow it doesn't (also not on my other project with STM32WB). But it does create a fresh FS after a full erase of the processors. Will try to test the PR #6904 to verify if this fixes the problem. |
|
Please put this temporarily on hold, a new board with USB connection does not yet function with this port. Need to add USB support correctly. |
Codecov Report
@@ Coverage Diff @@
## master #6911 +/- ##
==========================================
- Coverage 98.25% 98.24% -0.01%
==========================================
Files 154 154
Lines 20009 20009
==========================================
- Hits 19659 19657 -2
- Misses 350 352 +2
Continue to review full report at Codecov.
|
|
After a 'short' delay because of other priorities, we managed to get the USB mounting working on our own dev-board. This is now incorporated in the pull request. What we fixed in the last stages:
|
|
To my opinion all functionality is implemented. We've tested the G4 functionality on some of our own boards, and we fixed some issues. Next to our own boards, we also added the Nucleo G474 board for everyone to use. What can I do to help with this merge? |
|
Also tested with #8057 on Nucleo_G474 and own custom board with CAN connectivity. |
|
@dpgeorge / @chrismas9 I would like to get all ci checks in the green, but I don't think I could easily fix old commit messages to get them into the style of the Code Conventions (sorry my mistake...). If there is an easy way to fix them, could you point me in the right direction? |
|
Using |
I have looked into this, but that doesn't seem like the proper fix: I need to reword some commits from last year, and I just merged the master. If I reword my commits, I also (can) change the commits from the master (all hash-es change from the starting point, and I can change any commit message). And that is not what I want to. And I don't think the developers behind Micropython would like me to do this... Another way is to rebase the whole G4 change into the current master, but that is a lot of additional work, checks and tests, I don't think I can persuade my boss to let me do this for some commit-message fixes. |
|
Can you please rebase this on latest master? The new stm32lib was merged with G4 HAL support. |
214093d to
c650676
Compare
Rebased and reword applied. Tests currently running on Nucleo G474. |
|
Code formatting seems to have failed on an extra in ports/stm32/make-stmconst.py |
|
Thanks @H-Grobben for the effort on this, there is a lot of work here. I left some comments which are hopefully not too much work to respond to. If your time is short I can work them in during merge. Just let me know. |
|
Testing done. Still have issues with the ci_code_formatting_run on the ports/stm32/make-stmconst.py file. When running locally, some py files get extra newlines. But they are rejected by the github ci process. |
|
Tests showed that the RNG did not produce fully random numbers. This was caused by a clock issue on the RNG peripheral. Now the HSI48 is enabled and selected for RNG (and for future PR also for USB). |
|
Thanks for responding to the review comments. It looks like the CI failures are now gone, which is good! There are many commits in this PR and I will squash them all down into one during merge. |
|
Squashed and merged in 8f68e26 with the following minor changes (that did not change the compiled firmware image):
Thanks for the effort on this! |
| #define PYB_EXTI_NUM_VECTORS (42) // up to 42 event/interrupt requests: 28 configurable lines, 14 direct lines | ||
| #define MICROPY_HW_MAX_I2C (3) | ||
| #define MICROPY_HW_MAX_TIMER (20) // TIM 1-8, 20 | ||
| #define MICROPY_HW_MAX_UART (5) // uart 1 - 5 + lpuart1 |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
@H-Grobben I'm wondering if this should be 4, not 5. LPUART1 is excluded from this count, I think. Eg there is the following:
struct _pyb_uart_obj_t *pyb_uart_obj_all[MICROPY_HW_MAX_UART + MICROPY_HW_MAX_LPUART];
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
@dpgeorge It depends on the specific type. There are types with 3 USARTS (and LPUART) only, and the added Nucleo type (G474Rx) has 3 USARTS and 2 UARTS (and LPUART). I was in doubt on the number I should include here, but my decision was the number of peripherals in the Nucleo board, so that's why it was 5.
Check https://www.st.com/resource/en/datasheet/stm32g474re.pdf , page 15, Table 2.
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Ah, I see, thanks! So it is correct as is, it should be 5 because that is the maximum possible on the G4 series.
…-message touch up analogbufio ValueError msg
#6808 was closed due to a rename in out git repo, so I'm opening a new pull request on the new branch.
#5396: thanks for the pointer, I have tested it with the Nucleo G4 board.