[X86] Remove AMX-TF32#207673
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Add the removal in ReleaseNotes |
JaydeepChauhan14
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@llvm/pr-subscribers-llvm-ir @llvm/pr-subscribers-backend-x86 Author: Jaydeep Chauhan (JaydeepChauhan14) ChangesPer Intel Architecture Instruction Set Extensions Programming Reference rev. 62 https://cdrdv2.intel.com/v1/dl/getContent/922690 Revision History entry for revision -062 Patch is 32.81 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/207673.diff 34 Files Affected:
diff --git a/clang/docs/ReleaseNotes.md b/clang/docs/ReleaseNotes.md
index b7142ecb072ff..86f2e4738bbe1 100644
--- a/clang/docs/ReleaseNotes.md
+++ b/clang/docs/ReleaseNotes.md
@@ -927,6 +927,7 @@ latest release, please see the [Clang Web Site](https://clang.llvm.org) or the
- Support intrinsic of `_mm256_maskz_bitrev_epi8`.
- Support intrinsic of `_mm_bitrev_epi8`.
- Support intrinsic of `_mm256_bitrev_epi8`.
+- Removed support for `AMX-TF32` (`-mamx-tf32`) and `TMMULTF32PS` instruction.
#### Arm and AArch64 Support
diff --git a/clang/include/clang/Basic/BuiltinsX86_64.td b/clang/include/clang/Basic/BuiltinsX86_64.td
index baba21d47f93f..b323469c74d01 100644
--- a/clang/include/clang/Basic/BuiltinsX86_64.td
+++ b/clang/include/clang/Basic/BuiltinsX86_64.td
@@ -248,9 +248,6 @@ let Features = "amx-avx512,avx10.2", Attributes = [NoThrow, RequiredVectorWidth<
def tilemovrow_internal : X86Builtin<"_Vector<16, int>(unsigned short, unsigned short, _Vector<256, int>, unsigned int)">;
}
-let Features = "amx-tf32", Attributes = [NoThrow] in {
- def tmmultf32ps_internal : X86Builtin<"_Vector<256, int>(unsigned short, unsigned short, unsigned short, _Vector<256, int>, _Vector<256, int>, _Vector<256, int>)">;
-}
let Features = "amx-fp8", Attributes = [NoThrow] in {
def tdpbf8ps_internal : X86Builtin<"_Vector<256, int>(unsigned short, unsigned short, unsigned short, _Vector<256, int>, _Vector<256, int>, _Vector<256, int>)">;
@@ -323,10 +320,6 @@ let Features = "amx-fp8", Attributes = [NoThrow] in {
def tdphf8ps : X86Builtin<"void(_Constant unsigned char, unsigned _Constant char, unsigned _Constant char)">;
}
-let Features = "amx-tf32", Attributes = [NoThrow] in {
- def tmmultf32ps : X86Builtin<"void(_Constant unsigned char, _Constant unsigned char, _Constant unsigned char)">;
-}
-
let Features = "prefetchi", Attributes = [NoThrow, Const] in {
def prefetchi : X86Builtin<"void(void const *, unsigned int)">;
}
diff --git a/clang/include/clang/Options/Options.td b/clang/include/clang/Options/Options.td
index e6e8a46b846c8..23bb8d7d0c14a 100644
--- a/clang/include/clang/Options/Options.td
+++ b/clang/include/clang/Options/Options.td
@@ -7174,8 +7174,6 @@ def mamx_int8 : Flag<["-"], "mamx-int8">, Group<m_x86_Features_Group>;
def mno_amx_int8 : Flag<["-"], "mno-amx-int8">, Group<m_x86_Features_Group>;
def mamx_fp8 : Flag<["-"], "mamx-fp8">, Group<m_x86_Features_Group>;
def mno_amx_fp8 : Flag<["-"], "mno-amx-fp8">, Group<m_x86_Features_Group>;
-def mamx_tf32 : Flag<["-"], "mamx-tf32">, Group<m_x86_Features_Group>;
-def mno_amx_tf32 : Flag<["-"], "mno-amx-tf32">, Group<m_x86_Features_Group>;
def mamx_tile : Flag<["-"], "mamx-tile">, Group<m_x86_Features_Group>;
def mno_amx_tile : Flag<["-"], "mno-amx-tile">, Group<m_x86_Features_Group>;
def mamx_movrs: Flag<["-"], "mamx-movrs">, Group<m_x86_Features_Group>;
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index 9545367044555..d995ccabbcdc0 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -400,8 +400,6 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
HasAMXMOVRS = true;
} else if (Feature == "+amx-avx512") {
HasAMXAVX512 = true;
- } else if (Feature == "+amx-tf32") {
- HasAMXTF32 = true;
} else if (Feature == "+cmpccxadd") {
HasCMPCCXADD = true;
} else if (Feature == "+raoint") {
@@ -946,8 +944,6 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
Builder.defineMacro("__AMX_MOVRS__");
if (HasAMXAVX512)
Builder.defineMacro("__AMX_AVX512__");
- if (HasAMXTF32)
- Builder.defineMacro("__AMX_TF32__");
if (HasCMPCCXADD)
Builder.defineMacro("__CMPCCXADD__");
if (HasRAOINT)
@@ -1086,7 +1082,6 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
.Case("amx-fp8", true)
.Case("amx-int8", true)
.Case("amx-movrs", true)
- .Case("amx-tf32", true)
.Case("amx-tile", true)
.Case("avx", true)
.Case("avx10.1", true)
@@ -1208,7 +1203,6 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const {
.Case("amx-fp8", HasAMXFP8)
.Case("amx-int8", HasAMXINT8)
.Case("amx-movrs", HasAMXMOVRS)
- .Case("amx-tf32", HasAMXTF32)
.Case("amx-tile", HasAMXTILE)
.Case("avx", SSELevel >= AVX)
.Case("avx10.1", HasAVX10_1)
diff --git a/clang/lib/Basic/Targets/X86.h b/clang/lib/Basic/Targets/X86.h
index b0daffbea4576..a714d02f13048 100644
--- a/clang/lib/Basic/Targets/X86.h
+++ b/clang/lib/Basic/Targets/X86.h
@@ -164,7 +164,6 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo {
bool HasAMXFP8 = false;
bool HasAMXMOVRS = false;
bool HasAMXAVX512 = false;
- bool HasAMXTF32 = false;
bool HasSERIALIZE = false;
bool HasTSXLDTRK = false;
bool HasUSERMSR = false;
diff --git a/clang/lib/Headers/CMakeLists.txt b/clang/lib/Headers/CMakeLists.txt
index 0b50a966b6c0b..a4903ad3e03ec 100644
--- a/clang/lib/Headers/CMakeLists.txt
+++ b/clang/lib/Headers/CMakeLists.txt
@@ -176,7 +176,6 @@ set(x86_files
amxfp8intrin.h
amxintrin.h
amxmovrsintrin.h
- amxtf32intrin.h
avx10_2_512bf16intrin.h
avx10_2_512convertintrin.h
avx10_2_512minmaxintrin.h
diff --git a/clang/lib/Headers/amxtf32intrin.h b/clang/lib/Headers/amxtf32intrin.h
deleted file mode 100644
index 44d002c6600d6..0000000000000
--- a/clang/lib/Headers/amxtf32intrin.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/*===------------- amxtf32intrin.h - AMX_TF32 intrinsics -*- C++ -*---------===
- *
- * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
- * See https://llvm.org/LICENSE.txt for license information.
- * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
- *
- *===------------------------------------------------------------------------===
- */
-
-#ifndef __IMMINTRIN_H
-#error "Never use <amxtf32intrin.h> directly; include <immintrin.h> instead."
-#endif // __IMMINTRIN_H
-
-#ifndef __AMX_TF32INTRIN_H
-#define __AMX_TF32INTRIN_H
-#ifdef __x86_64__
-
-#define __DEFAULT_FN_ATTRS_TF32 \
- __attribute__((__always_inline__, __nodebug__, __target__("amx-tf32")))
-
-/// Do Matrix Multiplication of \a a and \a b, and then do Matrix Plus
-/// with \a srcdst.
-/// All the calculation is base on float32 but with the lower 13-bit set to 0.
-///
-/// \headerfile <immintrin.h>
-///
-/// \code
-/// void _tile_mmultf32ps(constexpr int srcdst, constexpr int a, \
-/// constexpr int b);
-/// \endcode
-///
-/// This intrinsic corresponds to the <c> TMMULTF32PS </c> instruction.
-///
-/// \param srcdst
-/// The destination tile. Max size is 1024 Bytes.
-/// \param a
-/// The 1st source tile. Max size is 1024 Bytes.
-/// \param b
-/// The 2nd source tile. Max size is 1024 Bytes.
-///
-/// \code{.operation}
-/// DEFINE zero_lower_mantissa_bits_fp32(x[31:0]) {
-/// dword[12:0] := 0
-/// dword[31:13] := x[31:13]
-/// return dword
-/// }
-///
-/// DEFINE silence_snan_fp32(x[31:0]) {
-/// IF (x.exponent == 255 and x.fraction != 0 and x.fraction[22] == 0)
-/// x.fraction[22] := 1
-/// return x
-/// }
-///
-/// elements_a := a.colsb / 4
-/// elements_dest := srcdst.colsb / 4
-///
-/// FOR m = 0 TO (srcdst.rows-1)
-/// tmp[511:0] := 0
-/// FOR k = 0 TO (elements_a-1)
-/// FOR n = 0 TO (elements_dest-1)
-/// af := silence_snan_fp32(a.row[m].fp32[k])
-/// bf := silence_snan_fp32(b.row[k].fp32[n])
-/// tmp.fp32[n] += zero_lower_mantissa_bits_fp32(af)
-/// * zero_lower_mantissa_bits_fp32(bf)
-/// ENDFOR
-/// ENDFOR
-///
-/// FOR n = 0 TO (elements_dest-1)
-/// tmp.fp32[n] += srcdst.row[m].fp32[n]
-/// ENDFOR
-/// write_row_and_zero(srcdst, m, tmp, srcdst.colsb)
-///
-/// ENDFOR
-///
-/// zero_upper_rows(srcdst, srcdst.rows)
-/// zero_tileconfig_start()
-/// \endcode
-#define _tile_mmultf32ps(srcdst, a, b) \
- __builtin_ia32_tmmultf32ps((srcdst), (a), (b))
-
-static __inline__ _tile1024i __DEFAULT_FN_ATTRS_TF32
-_tile_mmultf32ps_internal(unsigned short m, unsigned short n, unsigned short k,
- _tile1024i dst, _tile1024i src1, _tile1024i src2) {
- return __builtin_ia32_tmmultf32ps_internal(m, n, k, dst, src1, src2);
-}
-
-/// Do Matrix Multiplication of src0 and src1, and then do Matrix Plus with dst.
-/// All the calculation is base on float32 but with the lower 13-bit set to 0.
-///
-/// \headerfile <immintrin.h>
-///
-/// This intrinsic corresponds to the <c> TMMULTF32PS </c> instruction.
-///
-/// \param dst
-/// The destination tile. Max size is 1024 Bytes.
-/// \param src0
-/// The 1st source tile. Max size is 1024 Bytes.
-/// \param src1
-/// The 2nd source tile. Max size is 1024 Bytes.
-__DEFAULT_FN_ATTRS_TF32
-static void __tile_mmultf32ps(__tile1024i *dst, __tile1024i src0,
- __tile1024i src1) {
- dst->tile = _tile_mmultf32ps_internal(src0.row, src1.col, src0.col, dst->tile,
- src0.tile, src1.tile);
-}
-
-#endif // __x86_64__
-#endif // __AMX_TF32INTRIN_H
diff --git a/clang/lib/Headers/immintrin.h b/clang/lib/Headers/immintrin.h
index 00107c44c3a55..c9be46af22c29 100644
--- a/clang/lib/Headers/immintrin.h
+++ b/clang/lib/Headers/immintrin.h
@@ -483,8 +483,6 @@ _storebe_i64(void * __P, long long __D) {
#include <amxavx512intrin.h>
-#include <amxtf32intrin.h>
-
#include <avx512vp2intersectintrin.h>
#include <avx512vlvp2intersectintrin.h>
diff --git a/clang/lib/Sema/SemaX86.cpp b/clang/lib/Sema/SemaX86.cpp
index fa92d6ff122ee..cfd71d366e6fa 100644
--- a/clang/lib/Sema/SemaX86.cpp
+++ b/clang/lib/Sema/SemaX86.cpp
@@ -508,7 +508,6 @@ bool SemaX86::CheckBuiltinTileArguments(unsigned BuiltinID, CallExpr *TheCall) {
case X86::BI__builtin_ia32_tdpbhf8ps:
case X86::BI__builtin_ia32_tdphbf8ps:
case X86::BI__builtin_ia32_tdphf8ps:
- case X86::BI__builtin_ia32_tmmultf32ps:
return CheckBuiltinTileRangeAndDuplicate(TheCall, {0, 1, 2});
case X86::BI__builtin_ia32_tcvtrowps2bf16hi:
case X86::BI__builtin_ia32_tcvtrowps2bf16li:
diff --git a/clang/test/CodeGen/X86/amx_tf32.c b/clang/test/CodeGen/X86/amx_tf32.c
deleted file mode 100644
index 24893243b66e6..0000000000000
--- a/clang/test/CodeGen/X86/amx_tf32.c
+++ /dev/null
@@ -1,12 +0,0 @@
-// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +amx-tile -target-feature +amx-tf32 \
-// RUN: -emit-llvm -o - -Wall -Werror -pedantic -Wno-gnu-statement-expression | FileCheck %s
-
-#include <immintrin.h>
-#include <stddef.h>
-
-void test_tile_mmultf32ps(void) {
- // CHECK-LABEL: @test_tile_mmultf32ps(
- // CHECK: call void @llvm.x86.tmmultf32ps(i8 1, i8 2, i8 3)
- _tile_mmultf32ps(1, 2, 3);
-}
-
diff --git a/clang/test/CodeGen/X86/amx_tf32_api.c b/clang/test/CodeGen/X86/amx_tf32_api.c
deleted file mode 100644
index 531378dbd0d72..0000000000000
--- a/clang/test/CodeGen/X86/amx_tf32_api.c
+++ /dev/null
@@ -1,20 +0,0 @@
-// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=x86_64-unknown-unknown \
-// RUN: -target-feature +amx-tf32 \
-// RUN: -target-feature +amx-bf16 -target-feature +avx512f \
-// RUN: -emit-llvm -o - -Werror -pedantic | FileCheck %s
-
-#include <immintrin.h>
-
-char buf[1024];
-#define STRIDE 32
-
-char buf2[1024];
-
-void test_tile_mmultf32ps(__tile1024i a, __tile1024i b, __tile1024i c) {
- //CHECK-LABEL: @test_tile_mmultf32ps
- //CHECK-DAG: call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> {{%.*}})
- //CHECK-DAG: call x86_amx @llvm.x86.tmmultf32ps.internal
- //CHECK-DAG: call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx {{%.*}})
- __tile_mmultf32ps(&c, a, b);
-}
-
diff --git a/clang/test/CodeGen/X86/amx_tf32_errors.c b/clang/test/CodeGen/X86/amx_tf32_errors.c
deleted file mode 100644
index a1c525547c786..0000000000000
--- a/clang/test/CodeGen/X86/amx_tf32_errors.c
+++ /dev/null
@@ -1,15 +0,0 @@
-// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown \
-// RUN: -target-feature +amx-tf32 -verify
-
-#include <immintrin.h>
-#include <stddef.h>
-
-void test_tile_mmultf32ps() {
- _tile_mmultf32ps(16, 2, 3); // expected-error {{argument value 16 is outside the valid range [0, 7]}}
- _tile_mmultf32ps(1, 26, 3); // expected-error {{argument value 26 is outside the valid range [0, 7]}}
- _tile_mmultf32ps(1, 2, 36); // expected-error {{argument value 36 is outside the valid range [0, 7]}}
- _tile_mmultf32ps(1, 1, 3); // expected-error {{tile arguments must refer to different tiles}}
- _tile_mmultf32ps(1, 2, 1); // expected-error {{tile arguments must refer to different tiles}}
- _tile_mmultf32ps(1, 3, 3); // expected-error {{tile arguments must refer to different tiles}}
-}
-
diff --git a/clang/test/CodeGen/X86/amx_tf32_inline_asm.c b/clang/test/CodeGen/X86/amx_tf32_inline_asm.c
deleted file mode 100644
index ed67dda04e9f7..0000000000000
--- a/clang/test/CodeGen/X86/amx_tf32_inline_asm.c
+++ /dev/null
@@ -1,11 +0,0 @@
-// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +amx-tf32 -emit-llvm -o - -Wall -Werror -pedantic | FileCheck %s
-
-void f_tilemul(short a)
-{
- //CHECK: call void asm sideeffect "tileloadd 0(%rsi,%r13,4), %tmm0 \0A\09tileloadd 0(%rdx,%r14,4), %tmm6 \0A\09tmmultf32ps %tmm6, %tmm0, %tmm7 \0A\09tilestored %tmm7, 0(%r12,%r15,4) \0A\09", "~{memory},~{tmm0},~{tmm6},~{tmm7},~{dirflag},~{fpsr},~{flags}"()
- __asm__ volatile ("tileloadd 0(%%rsi,%%r13,4), %%tmm0 \n\t"
- "tileloadd 0(%%rdx,%%r14,4), %%tmm6 \n\t"
- "tmmultf32ps %%tmm6, %%tmm0, %%tmm7 \n\t"
- "tilestored %%tmm7, 0(%%r12,%%r15,4) \n\t"
- ::: "memory", "tmm0", "tmm6", "tmm7");
-}
diff --git a/clang/test/Driver/x86-target-features.c b/clang/test/Driver/x86-target-features.c
index 78b031ca4db5c..f18e820d15444 100644
--- a/clang/test/Driver/x86-target-features.c
+++ b/clang/test/Driver/x86-target-features.c
@@ -311,13 +311,6 @@
// AMX-AVX512: "-target-feature" "+amx-avx512"
// NO-AMX-AVX512: "-target-feature" "-amx-avx512"
-// RUN: %clang --target=x86_64-unknown-linux-gnu -mamx-tf32 %s \
-// RUN: -### -o %t.o 2>&1 | FileCheck -check-prefix=AMX-TF32 %s
-// RUN: %clang --target=x86_64-unknown-linux-gnu -mno-amx-tf32 %s \
-// RUN: -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-AMX-TF32 %s
-// AMX-TF32: "-target-feature" "+amx-tf32"
-// NO-AMX-TF32: "-target-feature" "-amx-tf32"
-
// RUN: %clang --target=i386 -march=i386 -mhreset %s -### 2>&1 | FileCheck -check-prefix=HRESET %s
// RUN: %clang --target=i386 -march=i386 -mno-hreset %s -### 2>&1 | FileCheck -check-prefix=NO-HRESET %s
// HRESET: "-target-feature" "+hreset"
diff --git a/clang/test/Preprocessor/predefined-arch-macros.c b/clang/test/Preprocessor/predefined-arch-macros.c
index dba8cf3d1af00..01a132d84daba 100644
--- a/clang/test/Preprocessor/predefined-arch-macros.c
+++ b/clang/test/Preprocessor/predefined-arch-macros.c
@@ -1839,7 +1839,6 @@
// CHECK_DMR_M32: #define __AMX_FP8__ 1
// CHECK_GNR_M32: #define __AMX_INT8__ 1
// CHECK_DMR_M32: #define __AMX_MOVRS__ 1
-// CHECK_DMR_M32: #define __AMX_TF32__ 1
// CHECK_GNR_M32: #define __AMX_TILE__ 1
// CHECK_DMR_M32: #define __AVX10_2_512__ 1
// CHECK_DMR_M32: #define __AVX10_2__ 1
@@ -1945,7 +1944,6 @@
// CHECK_DMR_M64: #define __AMX_FP8__ 1
// CHECK_GNR_M64: #define __AMX_INT8__ 1
// CHECK_DMR_M64: #define __AMX_MOVRS__ 1
-// CHECK_DMR_M64: #define __AMX_TF32__ 1
// CHECK_GNR_M64: #define __AMX_TILE__ 1
// CHECK_DMR_M64: #define __AVX10_2_512__ 1
// CHECK_DMR_M64: #define __AVX10_2__ 1
diff --git a/clang/test/Preprocessor/x86_target_features.c b/clang/test/Preprocessor/x86_target_features.c
index daf81d71e41c0..ac8ad64a46950 100644
--- a/clang/test/Preprocessor/x86_target_features.c
+++ b/clang/test/Preprocessor/x86_target_features.c
@@ -538,15 +538,6 @@
// NO-AMX-AVX512-NOT: #define __AMX_AVX512__ 1
-// RUN: %clang -target x86_64-unknown-linux-gnu -march=x86-64 -mamx-tf32 -x c \
-// RUN: -E -dM -o - %s | FileCheck -check-prefix=AMX-TF32 %s
-// AMX-TF32: #define __AMX_TF32__ 1
-// RUN: %clang -target x86_64-unknown-linux-gnu -march=x86-64 -mno-amx-tf32 -x c \
-// RUN: -E -dM -o - %s | FileCheck -check-prefix=NO-AMX-TF32 %s
-// RUN: %clang -target x86_64-unknown-linux-gnu -march=x86-64 -mamx-tf32 -mno-amx-tile \
-// RUN: -x c -E -dM -o - %s | FileCheck -check-prefix=NO-AMX-TF32 %s
-// NO-AMX-TF32-NOT: #define __AMX_TF32__ 1
-
// RUN: %clang -target i386-unknown-unknown -march=atom -mavxvnni -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVXVNNI %s
// AVXVNNI: #define __AVX2__ 1
diff --git a/compiler-rt/lib/builtins/cpu_model/x86.c b/compiler-rt/lib/builtins/cpu_model/x86.c
index 0323e0ba917e0..8320cc9f0d074 100644
--- a/compiler-rt/lib/builtins/cpu_model/x86.c
+++ b/compiler-rt/lib/builtins/cpu_model/x86.c
@@ -235,7 +235,6 @@ enum ProcessorFeatures {
FEATURE_AVX10_1 = 114,
FEATURE_AVX10_2 = 116,
FEATURE_AMX_AVX512,
- FEATURE_AMX_TF32,
FEATURE_AMX_FP8 = 120,
FEATURE_MOVRS,
FEATURE_AMX_MOVRS,
@@ -1146,8 +1145,6 @@ static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,
!getX86CpuIDAndInfoEx(0x1e, 0x1, &EAX, &EBX, &ECX, &EDX);
if (HasLeaf1E && (EAX & 0x10))
setFeature(FEATURE_AMX_FP8);
- if (HasLeaf1E && (EAX & 0x40))
- setFeature(FEATURE_AMX_TF32);
if (HasLeaf1E && (EAX & 0x80))
setFeature(FEATURE_AMX_AVX512);
if (HasLeaf1E && (EAX & 0x100))
diff --git a/llvm/include/llvm/IR/IntrinsicsX86.td b/llvm/include/llvm/IR/IntrinsicsX86.td
index 91ea6ee73191e..ad79a8dce3660 100644
--- a/llvm/include/llvm/IR/IntrinsicsX86.td
+++ b/llvm/include/llvm/IR/IntrinsicsX86.td
@@ -5652,16 +5652,6 @@ let TargetPrefix = "x86" in {
[llvm_i16_ty, llvm_i16_ty, llvm_x86amx_ty, llvm_i32_ty],
[]>;
- def int_x86_tmmultf32ps : ClangBuiltin<"__builtin_ia32_tmmultf32ps">,
- Intrinsic<[], [llvm_i8_ty, llvm_i8_ty, llvm_i8_ty],
- [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>,
- ImmArg<ArgIndex<2>>]>;
- def int_x86_tmmultf32ps_internal :
- ClangBuiltin<"__builtin_ia32_tmmultf32ps_internal">,
- Intrinsic<[llvm_x86amx_ty],
- [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_x86amx_ty,
- llvm_x86amx_ty, llvm_x86amx_ty], []>;
-
def int_x86_tdpbf8ps_internal :
ClangBuiltin<"__builtin_ia32_tdpbf8ps_internal">,
Intrinsic<[llvm_x86amx_ty],
diff --git a/llvm/include/llvm/TargetParser/X86TargetParser.def b/llvm/include/llvm/TargetParser/X86TargetParser.def
index 3db615204cf0a..355eb940d5cf3 100644
--- a/llvm/include/llvm/TargetParser/X86TargetParser.def
+++ b/llvm/include/llvm/TargetParser/X86TargetParser.def
@@ -249,7 +249,6 @@ X86_FEATURE_COMPAT(USERMSR, "usermsr", 0, 112)
X86_FEATURE_COMPAT(AVX10_1, "avx10.1", 34, 114)
X86_FEATURE_COMPAT(AVX10_2, "avx10.2", 35, 116)
X86_FEATURE_COMPAT(AMX_AVX512, "amx-avx512", 0, 117)
-X86_FEATURE_COMPAT(AMX_TF32, "amx-tf32", 0, 118)
X86_FEATURE_COMPAT(AMX_FP8, "amx-fp8", 0, 120)
X86_FEATURE_COMPAT(MOVRS, "movrs", 0, 121)
X86_FEATURE_COMPAT(AMX_MOVRS, "amx-movrs", 0, 122)
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index 56e9ab702c6d8..1496d3b4a8b22 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -297,9 +297,6 @@ def FeatureAMXAVX512 : SubtargetFeature<"amx-avx512",
"HasAMXAVX512", "true",
"Support AMX-AVX512 instructions",
[FeatureAMXTILE]>;
-def FeatureAMXTF32 : SubtargetFeature<"amx-tf32", "HasAMXTF32", "true",
- "Support AMX-TF32 instructions",
- [FeatureAMXTILE]>;
def FeatureCMPCCXADD : SubtargetFeature<"cmpccxadd", "HasCMPCCXADD", "true",
"Support CMPCCXADD instructions">;
def FeatureRAOINT : SubtargetFeature<"raoint", "HasRAOINT", "true",
@@ -1281,8 +1278,7 @@ def Pr...
[truncated]
|
🐧 Linux x64 Test Results
✅ The build succeeded and all tests passed. |
Contributor
|
@JaydeepChauhan14 please coordinate with #171172 |
e-kud
approved these changes
Jul 6, 2026
Contributor
Author
|
Ping @phoebewang |
aobolensk
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Per Intel Architecture Instruction Set Extensions Programming Reference rev. 62 https://cdrdv2.intel.com/v1/dl/getContent/922690 Revision History entry for revision -062
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Per Intel Architecture Instruction Set Extensions Programming Reference rev. 62 https://cdrdv2.intel.com/v1/dl/getContent/922690 Revision History entry for revision -062
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cleanup: upstream dropped AMX-TF32 LLVM recently dropped x86 AMX-TF32 llvm/llvm-project#207673. This is a cleanup similar to rust-lang#148338. @rustbot label llvm-main r? @durin42
3 tasks
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/95/builds/21521 Here is the relevant piece of the build log for the reference |
jhpratt
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…ingjubilee cleanup: upstream dropped AMX-TF32 LLVM recently dropped x86 AMX-TF32 llvm/llvm-project#207673. This is a re-upload of [rust-lang#158910](rust-lang#158910) as the author is out on vacation for this week. I've also removed the leftover references to amx-tf32 that were missed in the original PR which caused it to fail the roll up. r? @durin42
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Rollup merge of #159310 - gmittert:RmAmxTf32, r=sayantn,workingjubilee cleanup: upstream dropped AMX-TF32 LLVM recently dropped x86 AMX-TF32 llvm/llvm-project#207673. This is a re-upload of [#158910](#158910) as the author is out on vacation for this week. I've also removed the leftover references to amx-tf32 that were missed in the original PR which caused it to fail the roll up. r? @durin42
pull Bot
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Jul 16, 2026
cleanup: upstream dropped AMX-TF32 LLVM recently dropped x86 AMX-TF32 llvm/llvm-project#207673. This is a re-upload of [#158910](rust-lang/rust#158910) as the author is out on vacation for this week. I've also removed the leftover references to amx-tf32 that were missed in the original PR which caused it to fail the roll up. r? @durin42
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Per Intel Architecture Instruction Set Extensions Programming Reference rev. 62 https://cdrdv2.intel.com/v1/dl/getContent/922690 Revision History entry for revision -062