[RISCV][P-ext] Support v4i16/v2i32->v4i8/v2i16 truncate.#201757
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@llvm/pr-subscribers-backend-risc-v Author: Craig Topper (topperc) Changes5 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 690af51594056..891c8130c1c24 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -655,6 +655,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::MUL, {MVT::v4i16, MVT::v8i8}, Custom);
setOperationAction({ISD::SIGN_EXTEND, ISD::ZERO_EXTEND},
{MVT::v4i16, MVT::v2i32}, Legal);
+ setOperationAction(ISD::TRUNCATE, {MVT::v4i8, MVT::v2i16}, Legal);
setOperationAction(ISD::SETCC, P64VecVTs, Legal);
setCondCodeAction(
{ISD::SETGE, ISD::SETUGT, ISD::SETUGE, ISD::SETULE, ISD::SETLE},
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
index c2a8be1f17718..2e825ee698a2d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -2176,6 +2176,11 @@ let append Predicates = [IsRV32] in {
def : Pat<(v2i16 (build_vector (XLenVT GPR:$a), (XLenVT GPR:$b))),
(PACK GPR:$a, GPR:$b)>;
+ // Truncate patterns using pnsrli.
+ // FIXME: Support general shift+trunc
+ def : Pat<(v4i8 (trunc (v4i16 GPRPair:$rs))), (PNSRLI_B GPRPair:$rs, 0)>;
+ def : Pat<(v2i16 (trunc (v2i32 GPRPair:$rs))), (PNSRLI_H GPRPair:$rs, 0)>;
+
// Basic 8-bit arithmetic patterns
def : PatGprPairGprPair<add, PADD_DB, v8i8>;
def : PatGprPairGprPair<sub, PSUB_DB, v8i8>;
diff --git a/llvm/test/CodeGen/RISCV/rvp-narrowing-shift-trunc.ll b/llvm/test/CodeGen/RISCV/rvp-narrowing-shift-trunc.ll
index a4a70da07f95c..c4febc2cc317b 100644
--- a/llvm/test/CodeGen/RISCV/rvp-narrowing-shift-trunc.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-narrowing-shift-trunc.ll
@@ -13,7 +13,7 @@ define i32 @trunc_lshr_v2i32_to_v2i16(i64 %a.coerce) {
; CHECK-RV32-LABEL: trunc_lshr_v2i32_to_v2i16:
; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: psrli.dw a0, a0, 8
-; CHECK-RV32-NEXT: pack a0, a0, a1
+; CHECK-RV32-NEXT: pncvt.h a0, a0
; CHECK-RV32-NEXT: ret
;
; CHECK-RV64-LABEL: trunc_lshr_v2i32_to_v2i16:
@@ -33,7 +33,7 @@ define i32 @trunc_ashr_v2i32_to_v2i16(i64 %a.coerce) {
; CHECK-RV32-LABEL: trunc_ashr_v2i32_to_v2i16:
; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: psrli.dw a0, a0, 8
-; CHECK-RV32-NEXT: pack a0, a0, a1
+; CHECK-RV32-NEXT: pncvt.h a0, a0
; CHECK-RV32-NEXT: ret
;
; CHECK-RV64-LABEL: trunc_ashr_v2i32_to_v2i16:
@@ -53,10 +53,7 @@ define i32 @trunc_lshr_v4i16_to_v4i8(i64 %a.coerce) {
; CHECK-RV32-LABEL: trunc_lshr_v4i16_to_v4i8:
; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: psrli.dh a0, a0, 4
-; CHECK-RV32-NEXT: srli a3, a1, 16
-; CHECK-RV32-NEXT: srli a2, a0, 16
-; CHECK-RV32-NEXT: ppaire.db a0, a0, a2
-; CHECK-RV32-NEXT: pack a0, a0, a1
+; CHECK-RV32-NEXT: pncvt.b a0, a0
; CHECK-RV32-NEXT: ret
;
; CHECK-RV64-LABEL: trunc_lshr_v4i16_to_v4i8:
diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-32.ll b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
index 708df92cdd2c2..f73b8a44a0cbd 100644
--- a/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
@@ -1275,10 +1275,7 @@ define <4 x i8> @test_pmulhsu_b(<4 x i8> %a, <4 x i8> %b) {
; RV32-NEXT: pwmul.h a2, a2, a0
; RV32-NEXT: pncvt.h a0, a2
; RV32-NEXT: psrli.dh a0, a0, 8
-; RV32-NEXT: srli a3, a1, 16
-; RV32-NEXT: srli a2, a0, 16
-; RV32-NEXT: ppaire.db a0, a0, a2
-; RV32-NEXT: pack a0, a0, a1
+; RV32-NEXT: pncvt.b a0, a0
; RV32-NEXT: ret
;
; RV64-LABEL: test_pmulhsu_b:
@@ -1316,10 +1313,7 @@ define <4 x i8> @test_pmulhsu_b_commuted(<4 x i8> %a, <4 x i8> %b) {
; RV32-NEXT: pwmul.h a2, a2, a0
; RV32-NEXT: pncvt.h a0, a2
; RV32-NEXT: psrli.dh a0, a0, 8
-; RV32-NEXT: srli a3, a1, 16
-; RV32-NEXT: srli a2, a0, 16
-; RV32-NEXT: ppaire.db a0, a0, a2
-; RV32-NEXT: pack a0, a0, a1
+; RV32-NEXT: pncvt.b a0, a0
; RV32-NEXT: ret
;
; RV64-LABEL: test_pmulhsu_b_commuted:
diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
index bcb48f5dcfc74..337eec6e45bbf 100644
--- a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
@@ -2220,18 +2220,10 @@ define <8 x i8> @test_pmulh_b(<8 x i8> %a, <8 x i8> %b) {
; RV32-NEXT: pncvt.h a3, a2
; RV32-NEXT: pncvt.h a6, a0
; RV32-NEXT: pncvt.h a2, a4
-; RV32-NEXT: psrli.dh a0, a2, 8
-; RV32-NEXT: psrli.dh a2, a6, 8
-; RV32-NEXT: srli a4, a3, 16
-; RV32-NEXT: srli a5, a2, 16
-; RV32-NEXT: srli a6, a1, 16
-; RV32-NEXT: srli a7, a0, 16
-; RV32-NEXT: ppaire.b a3, a3, a4
-; RV32-NEXT: ppaire.b a2, a2, a5
-; RV32-NEXT: ppaire.b a4, a1, a6
-; RV32-NEXT: ppaire.b a0, a0, a7
-; RV32-NEXT: pack a1, a2, a3
-; RV32-NEXT: pack a0, a0, a4
+; RV32-NEXT: psrli.dh a2, a2, 8
+; RV32-NEXT: psrli.dh a0, a6, 8
+; RV32-NEXT: pncvt.b a1, a0
+; RV32-NEXT: pncvt.b a0, a2
; RV32-NEXT: ret
;
; RV64-LABEL: test_pmulh_b:
@@ -2302,18 +2294,10 @@ define <8 x i8> @test_pmulhu_b(<8 x i8> %a, <8 x i8> %b) {
; RV32-NEXT: pncvt.h a3, a2
; RV32-NEXT: pncvt.h a6, a0
; RV32-NEXT: pncvt.h a2, a4
-; RV32-NEXT: psrli.dh a0, a2, 8
-; RV32-NEXT: psrli.dh a2, a6, 8
-; RV32-NEXT: srli a4, a3, 16
-; RV32-NEXT: srli a5, a2, 16
-; RV32-NEXT: srli a6, a1, 16
-; RV32-NEXT: srli a7, a0, 16
-; RV32-NEXT: ppaire.b a3, a3, a4
-; RV32-NEXT: ppaire.b a2, a2, a5
-; RV32-NEXT: ppaire.b a4, a1, a6
-; RV32-NEXT: ppaire.b a0, a0, a7
-; RV32-NEXT: pack a1, a2, a3
-; RV32-NEXT: pack a0, a0, a4
+; RV32-NEXT: psrli.dh a2, a2, 8
+; RV32-NEXT: psrli.dh a0, a6, 8
+; RV32-NEXT: pncvt.b a1, a0
+; RV32-NEXT: pncvt.b a0, a2
; RV32-NEXT: ret
;
; RV64-LABEL: test_pmulhu_b:
@@ -2383,18 +2367,10 @@ define <8 x i8> @test_pmulhsu_b(<8 x i8> %a, <8 x i8> %b) {
; RV32-NEXT: pncvt.h a3, a2
; RV32-NEXT: pncvt.h a6, a0
; RV32-NEXT: pncvt.h a2, a4
-; RV32-NEXT: psrli.dh a0, a2, 8
-; RV32-NEXT: psrli.dh a2, a6, 8
-; RV32-NEXT: srli a4, a3, 16
-; RV32-NEXT: srli a5, a2, 16
-; RV32-NEXT: srli a6, a1, 16
-; RV32-NEXT: srli a7, a0, 16
-; RV32-NEXT: ppaire.b a3, a3, a4
-; RV32-NEXT: ppaire.b a2, a2, a5
-; RV32-NEXT: ppaire.b a4, a1, a6
-; RV32-NEXT: ppaire.b a0, a0, a7
-; RV32-NEXT: pack a1, a2, a3
-; RV32-NEXT: pack a0, a0, a4
+; RV32-NEXT: psrli.dh a2, a2, 8
+; RV32-NEXT: psrli.dh a0, a6, 8
+; RV32-NEXT: pncvt.b a1, a0
+; RV32-NEXT: pncvt.b a0, a2
; RV32-NEXT: ret
;
; RV64-LABEL: test_pmulhsu_b:
@@ -2466,18 +2442,10 @@ define <8 x i8> @test_pmulhsu_b_commuted(<8 x i8> %a, <8 x i8> %b) {
; RV32-NEXT: pncvt.h a3, a2
; RV32-NEXT: pncvt.h a6, a0
; RV32-NEXT: pncvt.h a2, a4
-; RV32-NEXT: psrli.dh a0, a2, 8
-; RV32-NEXT: psrli.dh a2, a6, 8
-; RV32-NEXT: srli a4, a3, 16
-; RV32-NEXT: srli a5, a2, 16
-; RV32-NEXT: srli a6, a1, 16
-; RV32-NEXT: srli a7, a0, 16
-; RV32-NEXT: ppaire.b a3, a3, a4
-; RV32-NEXT: ppaire.b a2, a2, a5
-; RV32-NEXT: ppaire.b a4, a1, a6
-; RV32-NEXT: ppaire.b a0, a0, a7
-; RV32-NEXT: pack a1, a2, a3
-; RV32-NEXT: pack a0, a0, a4
+; RV32-NEXT: psrli.dh a2, a2, 8
+; RV32-NEXT: psrli.dh a0, a6, 8
+; RV32-NEXT: pncvt.b a1, a0
+; RV32-NEXT: pncvt.b a0, a2
; RV32-NEXT: ret
;
; RV64-LABEL: test_pmulhsu_b_commuted:
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