[RISCV] Use a vector MemVT when converting store+extractelt into a vector store.#190107
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@llvm/pr-subscribers-backend-risc-v Author: Craig Topper (topperc) ChangesThis is needed so that we check for unaligned vector memory While there remove incorrect setting of the truncating store flag Fixes #189037 2 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index fff62837ee310..d137794c0450f 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -22435,16 +22435,18 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
SDValue Src = Val.getOperand(0);
MVT VecVT = Src.getSimpleValueType();
// VecVT should be scalable and memory VT should match the element type.
- if (!Store->isIndexed() && VecVT.isScalableVector() &&
- MemVT == VecVT.getVectorElementType()) {
+ if (!Store->isIndexed() && Store->isSimple() &&
+ VecVT.isScalableVector() && MemVT == VecVT.getVectorElementType()) {
SDLoc DL(N);
MVT MaskVT = getMaskTypeFor(VecVT);
+ // Create a vector memory VT so allowsMisalignedMemoryAccesses will
+ // work correctly.
+ MemVT = EVT::getVectorVT(*DAG.getContext(), MemVT, 1);
return DAG.getStoreVP(
Store->getChain(), DL, Src, Store->getBasePtr(), Store->getOffset(),
DAG.getConstant(1, DL, MaskVT),
DAG.getConstant(1, DL, Subtarget.getXLenVT()), MemVT,
- Store->getMemOperand(), Store->getAddressingMode(),
- Store->isTruncatingStore(), /*IsCompress*/ false);
+ Store->getMemOperand(), Store->getAddressingMode());
}
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/pr189037.ll b/llvm/test/CodeGen/RISCV/rvv/pr189037.ll
new file mode 100644
index 0000000000000..a5707a46bbec3
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/pr189037.ll
@@ -0,0 +1,40 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+unaligned-scalar-mem | FileCheck %s
+
+define void @test_load_store_vec_align1(ptr %0, ptr %1, i64 %2, i64 %3, i64 %4, ptr %out) {
+; CHECK-LABEL: test_load_store_vec_align1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: slli a3, a3, 1
+; CHECK-NEXT: add a0, a0, a3
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: add a4, a5, a4
+; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; CHECK-NEXT: vse8.v v8, (a4)
+; CHECK-NEXT: ret
+ %arrayidx.i.i.i = getelementptr inbounds <2 x i8>, ptr %0, i64 %3
+ %19 = load <1 x i16>, ptr %arrayidx.i.i.i, align 1
+ %coerce.val.ii.i = extractelement <1 x i16> %19, i64 0
+ %arrayidx.i = getelementptr inbounds nuw i8, ptr %out, i64 %4
+ store i16 %coerce.val.ii.i, ptr %arrayidx.i, align 1
+ ret void
+}
+
+define void @test_load_store_vec_align2(ptr %0, ptr %1, i64 %2, i64 %3, i64 %4, ptr %out) {
+; CHECK-LABEL: test_load_store_vec_align2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: slli a3, a3, 1
+; CHECK-NEXT: add a0, a0, a3
+; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: add a4, a5, a4
+; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; CHECK-NEXT: vse8.v v8, (a4)
+; CHECK-NEXT: ret
+ %arrayidx.i.i.i = getelementptr inbounds <2 x i8>, ptr %0, i64 %3
+ %19 = load <1 x i16>, ptr %arrayidx.i.i.i, align 2
+ %coerce.val.ii.i = extractelement <1 x i16> %19, i64 0
+ %arrayidx.i = getelementptr inbounds nuw i8, ptr %out, i64 %4
+ store i16 %coerce.val.ii.i, ptr %arrayidx.i, align 1
+ ret void
+}
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lukel97
reviewed
Apr 2, 2026
…ctor store. This is needed so that we check for unaligned vector memory support unaligned scalar memory support. While there remove incorrect setting of the truncating store flag on the vector instruction. And restrict the transform to simple stores since we don't have tests for volatile or atomic. Fixes llvm#189037
lukel97
approved these changes
Apr 2, 2026
c-rhodes
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Apr 7, 2026
…ctor store. (#190107) This is needed so that `allowsMemoryAccessForAlignment` checks for unaligned vector memory support instead of unaligned scalar memory support when called from `RISCVTargetLowering::expandUnalignedVPStore` While there remove incorrect setting of the truncating store flag on the vector instruction. And restrict the transform to simple stores since we don't have tests for volatile or atomic. Fixes #189037 (cherry picked from commit b44d2c9)
zwu-2025
pushed a commit
to zwu-2025/llvm-project
that referenced
this pull request
May 17, 2026
…ctor store. (llvm#190107) This is needed so that `allowsMemoryAccessForAlignment` checks for unaligned vector memory support instead of unaligned scalar memory support when called from `RISCVTargetLowering::expandUnalignedVPStore` While there remove incorrect setting of the truncating store flag on the vector instruction. And restrict the transform to simple stores since we don't have tests for volatile or atomic. Fixes llvm#189037
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This is needed so that
allowsMemoryAccessForAlignmentchecks for unaligned vector memorysupport instead of unaligned scalar memory support when called from
RISCVTargetLowering::expandUnalignedVPStoreWhile there remove incorrect setting of the truncating store flag
on the vector instruction. And restrict the transform to simple stores
since we don't have tests for volatile or atomic.
Fixes #189037