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[RISCV][llvm] Correct code generation of fma on zvfbfa#176716

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4vtomat merged 1 commit intollvm:mainfrom
4vtomat:zvfbfa_vfmadd_bug
Jan 21, 2026
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[RISCV][llvm] Correct code generation of fma on zvfbfa#176716
4vtomat merged 1 commit intollvm:mainfrom
4vtomat:zvfbfa_vfmadd_bug

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@4vtomat 4vtomat commented Jan 19, 2026

Currently it's mapped to normal float16 instructions.

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[RISCV][llvm] Correct code generation of fma on zvfbfa
2028a8b 
Currently it's mapped to normal float16 instructions.
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llvmbot commented Jan 19, 2026

@llvm/pr-subscribers-backend-risc-v

Author: Brandon Wu (4vtomat)

Changes

Currently it's mapped to normal float16 instructions.

Patch is 64.54 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/176716.diff

10 Files Affected:

  • (modified) llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td (+11-10)
  • (modified) llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td (+3-2)
  • (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmadd-sdnode.ll (+20-20)
  • (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsub-sdnode.ll (+20-20)
  • (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmadd-sdnode.ll (+20-20)
  • (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmsub-sdnode.ll (+20-20)
  • (modified) llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll (+13-13)
  • (modified) llvm/test/CodeGen/RISCV/rvv/vfmsub-sdnode.ll (+12-12)
  • (modified) llvm/test/CodeGen/RISCV/rvv/vfnmadd-sdnode.ll (+12-12)
  • (modified) llvm/test/CodeGen/RISCV/rvv/vfnmsub-sdnode.ll (+12-12)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
index 1bdbfe40b1521..4a57b7f7f15b3 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -1233,10 +1233,11 @@ foreach fvti = AllFloatAndBF16Vectors in {
   // NOTE: We choose VFMADD because it has the most commuting freedom. So it
   // works best with how TwoAddressInstructionPass tries commuting.
   defvar suffix = fvti.LMul.MX # "_E" # fvti.SEW;
+  defvar alt = !if(!eq(fvti.Scalar, bf16), "_ALT", "");
   let Predicates = GetVTypePredicates<fvti>.Predicates in {
     def : Pat<(fvti.Vector (any_fma fvti.RegClass:$rs1, fvti.RegClass:$rd,
                                     fvti.RegClass:$rs2)),
-              (!cast<Instruction>("PseudoVFMADD_VV_"# suffix)
+              (!cast<Instruction>("PseudoVFMADD" # alt # "_VV_"# suffix)
                    fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2,
                    // Value to indicate no rounding mode change in
                    // RISCVInsertReadWriteCSR
@@ -1244,7 +1245,7 @@ foreach fvti = AllFloatAndBF16Vectors in {
                    fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>;
     def : Pat<(fvti.Vector (any_fma fvti.RegClass:$rs1, fvti.RegClass:$rd,
                                     (fneg fvti.RegClass:$rs2))),
-              (!cast<Instruction>("PseudoVFMSUB_VV_"# suffix)
+              (!cast<Instruction>("PseudoVFMSUB" # alt # "_VV_"# suffix)
                    fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2,
                    // Value to indicate no rounding mode change in
                    // RISCVInsertReadWriteCSR
@@ -1252,7 +1253,7 @@ foreach fvti = AllFloatAndBF16Vectors in {
                    fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>;
     def : Pat<(fvti.Vector (any_fma (fneg fvti.RegClass:$rs1), fvti.RegClass:$rd,
                                     (fneg fvti.RegClass:$rs2))),
-              (!cast<Instruction>("PseudoVFNMADD_VV_"# suffix)
+              (!cast<Instruction>("PseudoVFNMADD" # alt # "_VV_"# suffix)
                    fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2,
                    // Value to indicate no rounding mode change in
                    // RISCVInsertReadWriteCSR
@@ -1260,7 +1261,7 @@ foreach fvti = AllFloatAndBF16Vectors in {
                    fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>;
     def : Pat<(fvti.Vector (any_fma (fneg fvti.RegClass:$rs1), fvti.RegClass:$rd,
                                     fvti.RegClass:$rs2)),
-              (!cast<Instruction>("PseudoVFNMSUB_VV_"# suffix)
+              (!cast<Instruction>("PseudoVFNMSUB" # alt # "_VV_"# suffix)
                    fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2,
                    // Value to indicate no rounding mode change in
                    // RISCVInsertReadWriteCSR
@@ -1271,7 +1272,7 @@ foreach fvti = AllFloatAndBF16Vectors in {
     // commutable.
     def : Pat<(fvti.Vector (any_fma (SplatFPOp fvti.ScalarRegClass:$rs1),
                                     fvti.RegClass:$rd, fvti.RegClass:$rs2)),
-              (!cast<Instruction>("PseudoVFMADD_V" # fvti.ScalarSuffix # "_" # suffix)
+              (!cast<Instruction>("PseudoVFMADD" # alt # "_V" # fvti.ScalarSuffix # "_" # suffix)
                    fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2,
                    // Value to indicate no rounding mode change in
                    // RISCVInsertReadWriteCSR
@@ -1279,7 +1280,7 @@ foreach fvti = AllFloatAndBF16Vectors in {
                    fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>;
     def : Pat<(fvti.Vector (any_fma (SplatFPOp fvti.ScalarRegClass:$rs1),
                                     fvti.RegClass:$rd, (fneg fvti.RegClass:$rs2))),
-              (!cast<Instruction>("PseudoVFMSUB_V" # fvti.ScalarSuffix # "_" # suffix)
+              (!cast<Instruction>("PseudoVFMSUB" # alt # "_V" # fvti.ScalarSuffix # "_" # suffix)
                    fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2,
                    // Value to indicate no rounding mode change in
                    // RISCVInsertReadWriteCSR
@@ -1288,7 +1289,7 @@ foreach fvti = AllFloatAndBF16Vectors in {
 
     def : Pat<(fvti.Vector (any_fma (SplatFPOp fvti.ScalarRegClass:$rs1),
                                     (fneg fvti.RegClass:$rd), (fneg fvti.RegClass:$rs2))),
-              (!cast<Instruction>("PseudoVFNMADD_V" # fvti.ScalarSuffix # "_" # suffix)
+              (!cast<Instruction>("PseudoVFNMADD" # alt # "_V" # fvti.ScalarSuffix # "_" # suffix)
                    fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2,
                    // Value to indicate no rounding mode change in
                    // RISCVInsertReadWriteCSR
@@ -1296,7 +1297,7 @@ foreach fvti = AllFloatAndBF16Vectors in {
                    fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>;
     def : Pat<(fvti.Vector (any_fma (SplatFPOp fvti.ScalarRegClass:$rs1),
                                     (fneg fvti.RegClass:$rd), fvti.RegClass:$rs2)),
-              (!cast<Instruction>("PseudoVFNMSUB_V" # fvti.ScalarSuffix # "_" # suffix)
+              (!cast<Instruction>("PseudoVFNMSUB" # alt # "_V" # fvti.ScalarSuffix # "_" # suffix)
                    fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2,
                    // Value to indicate no rounding mode change in
                    // RISCVInsertReadWriteCSR
@@ -1306,7 +1307,7 @@ foreach fvti = AllFloatAndBF16Vectors in {
     // The splat might be negated.
     def : Pat<(fvti.Vector (any_fma (fneg (SplatFPOp fvti.ScalarRegClass:$rs1)),
                                     fvti.RegClass:$rd, (fneg fvti.RegClass:$rs2))),
-              (!cast<Instruction>("PseudoVFNMADD_V" # fvti.ScalarSuffix # "_" # suffix)
+              (!cast<Instruction>("PseudoVFNMADD" # alt # "_V" # fvti.ScalarSuffix # "_" # suffix)
                    fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2,
                    // Value to indicate no rounding mode change in
                    // RISCVInsertReadWriteCSR
@@ -1314,7 +1315,7 @@ foreach fvti = AllFloatAndBF16Vectors in {
                    fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>;
     def : Pat<(fvti.Vector (any_fma (fneg (SplatFPOp fvti.ScalarRegClass:$rs1)),
                                     fvti.RegClass:$rd, fvti.RegClass:$rs2)),
-              (!cast<Instruction>("PseudoVFNMSUB_V" # fvti.ScalarSuffix # "_" # suffix)
+              (!cast<Instruction>("PseudoVFNMSUB" # alt # "_V" # fvti.ScalarSuffix # "_" # suffix)
                    fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2,
                    // Value to indicate no rounding mode change in
                    // RISCVInsertReadWriteCSR
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index f57f84684f7bb..b729f3e63e8d0 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -1814,11 +1814,12 @@ multiclass VPatFPMulAddVL_VV_VF<SDPatternOperator vop, string instruction_name>
 multiclass VPatFPMulAddVL_VV_VF_RM<SDPatternOperator vop, string instruction_name> {
   foreach vti = AllFloatAndBF16Vectors in {
   defvar suffix = vti.LMul.MX # "_E" # vti.SEW;
+  defvar alt = !if(!eq(vti.Scalar, bf16), "_ALT", "");
   let Predicates = GetVTypePredicates<vti>.Predicates in {
     def : Pat<(vti.Vector (vop vti.RegClass:$rs1, vti.RegClass:$rd,
                                vti.RegClass:$rs2, (vti.Mask VMV0:$vm),
                                VLOpFrag)),
-              (!cast<Instruction>(instruction_name#"_VV_"# suffix #"_MASK")
+              (!cast<Instruction>(instruction_name # alt # "_VV_"# suffix #"_MASK")
                    vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
                    (vti.Mask VMV0:$vm),
                    // Value to indicate no rounding mode change in
@@ -1830,7 +1831,7 @@ multiclass VPatFPMulAddVL_VV_VF_RM<SDPatternOperator vop, string instruction_nam
                                vti.RegClass:$rd, vti.RegClass:$rs2,
                                (vti.Mask VMV0:$vm),
                                VLOpFrag)),
-              (!cast<Instruction>(instruction_name#"_V" # vti.ScalarSuffix # "_" # suffix # "_MASK")
+              (!cast<Instruction>(instruction_name # alt # "_V" # vti.ScalarSuffix # "_" # suffix # "_MASK")
                    vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
                    (vti.Mask VMV0:$vm),
                    // Value to indicate no rounding mode change in
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmadd-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmadd-sdnode.ll
index 814ee7739ee62..89cf847bb2c70 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmadd-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmadd-sdnode.ll
@@ -7,7 +7,7 @@
 define <1 x bfloat> @vfmadd_vv_v1bf16(<1 x bfloat> %va, <1 x bfloat> %vb, <1 x bfloat> %vc) {
 ; CHECK-LABEL: vfmadd_vv_v1bf16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
+; CHECK-NEXT:    vsetivli zero, 1, e16alt, mf4, ta, ma
 ; CHECK-NEXT:    vfmadd.vv v8, v9, v10
 ; CHECK-NEXT:    ret
   %vd = call <1 x bfloat> @llvm.fma.v1bf16(<1 x bfloat> %va, <1 x bfloat> %vb, <1 x bfloat> %vc)
@@ -17,7 +17,7 @@ define <1 x bfloat> @vfmadd_vv_v1bf16(<1 x bfloat> %va, <1 x bfloat> %vb, <1 x b
 define <1 x bfloat> @vfmadd_vf_v1bf16(<1 x bfloat> %va, <1 x bfloat> %vb, bfloat %c) {
 ; CHECK-LABEL: vfmadd_vf_v1bf16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
+; CHECK-NEXT:    vsetivli zero, 1, e16alt, mf4, ta, ma
 ; CHECK-NEXT:    vfmadd.vf v8, fa0, v9
 ; CHECK-NEXT:    ret
   %head = insertelement <1 x bfloat> poison, bfloat %c, i32 0
@@ -29,7 +29,7 @@ define <1 x bfloat> @vfmadd_vf_v1bf16(<1 x bfloat> %va, <1 x bfloat> %vb, bfloat
 define <2 x bfloat> @vfmadd_vv_v2bf16(<2 x bfloat> %va, <2 x bfloat> %vb, <2 x bfloat> %vc) {
 ; CHECK-LABEL: vfmadd_vv_v2bf16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT:    vsetivli zero, 2, e16alt, mf4, ta, ma
 ; CHECK-NEXT:    vfmadd.vv v8, v9, v10
 ; CHECK-NEXT:    ret
   %vd = call <2 x bfloat> @llvm.fma.v2bf16(<2 x bfloat> %va, <2 x bfloat> %vb, <2 x bfloat> %vc)
@@ -39,7 +39,7 @@ define <2 x bfloat> @vfmadd_vv_v2bf16(<2 x bfloat> %va, <2 x bfloat> %vb, <2 x b
 define <2 x bfloat> @vfmadd_vf_v2bf16(<2 x bfloat> %va, <2 x bfloat> %vb, bfloat %c) {
 ; CHECK-LABEL: vfmadd_vf_v2bf16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT:    vsetivli zero, 2, e16alt, mf4, ta, ma
 ; CHECK-NEXT:    vfmadd.vf v8, fa0, v9
 ; CHECK-NEXT:    ret
   %head = insertelement <2 x bfloat> poison, bfloat %c, i32 0
@@ -51,7 +51,7 @@ define <2 x bfloat> @vfmadd_vf_v2bf16(<2 x bfloat> %va, <2 x bfloat> %vb, bfloat
 define <4 x bfloat> @vfmadd_vv_v4bf16(<4 x bfloat> %va, <4 x bfloat> %vb, <4 x bfloat> %vc) {
 ; CHECK-LABEL: vfmadd_vv_v4bf16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT:    vsetivli zero, 4, e16alt, mf2, ta, ma
 ; CHECK-NEXT:    vfmadd.vv v8, v9, v10
 ; CHECK-NEXT:    ret
   %vd = call <4 x bfloat> @llvm.fma.v4bf16(<4 x bfloat> %va, <4 x bfloat> %vb, <4 x bfloat> %vc)
@@ -61,7 +61,7 @@ define <4 x bfloat> @vfmadd_vv_v4bf16(<4 x bfloat> %va, <4 x bfloat> %vb, <4 x b
 define <4 x bfloat> @vfmadd_vf_v4bf16(<4 x bfloat> %va, <4 x bfloat> %vb, bfloat %c) {
 ; CHECK-LABEL: vfmadd_vf_v4bf16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT:    vsetivli zero, 4, e16alt, mf2, ta, ma
 ; CHECK-NEXT:    vfmadd.vf v8, fa0, v9
 ; CHECK-NEXT:    ret
   %head = insertelement <4 x bfloat> poison, bfloat %c, i32 0
@@ -73,7 +73,7 @@ define <4 x bfloat> @vfmadd_vf_v4bf16(<4 x bfloat> %va, <4 x bfloat> %vb, bfloat
 define <8 x bfloat> @vfmadd_vv_v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, <8 x bfloat> %vc) {
 ; CHECK-LABEL: vfmadd_vv_v8bf16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vsetivli zero, 8, e16alt, m1, ta, ma
 ; CHECK-NEXT:    vfmadd.vv v8, v9, v10
 ; CHECK-NEXT:    ret
   %vd = call <8 x bfloat> @llvm.fma.v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, <8 x bfloat> %vc)
@@ -83,7 +83,7 @@ define <8 x bfloat> @vfmadd_vv_v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, <8 x b
 define <8 x bfloat> @vfmadd_vf_v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, bfloat %c) {
 ; CHECK-LABEL: vfmadd_vf_v8bf16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vsetivli zero, 8, e16alt, m1, ta, ma
 ; CHECK-NEXT:    vfmadd.vf v8, fa0, v9
 ; CHECK-NEXT:    ret
   %head = insertelement <8 x bfloat> poison, bfloat %c, i32 0
@@ -95,7 +95,7 @@ define <8 x bfloat> @vfmadd_vf_v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, bfloat
 define <16 x bfloat> @vfmadd_vv_v16bf16(<16 x bfloat> %va, <16 x bfloat> %vb, <16 x bfloat> %vc) {
 ; CHECK-LABEL: vfmadd_vv_v16bf16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT:    vsetivli zero, 16, e16alt, m2, ta, ma
 ; CHECK-NEXT:    vfmadd.vv v8, v10, v12
 ; CHECK-NEXT:    ret
   %vd = call <16 x bfloat> @llvm.fma.v16bf16(<16 x bfloat> %va, <16 x bfloat> %vb, <16 x bfloat> %vc)
@@ -105,7 +105,7 @@ define <16 x bfloat> @vfmadd_vv_v16bf16(<16 x bfloat> %va, <16 x bfloat> %vb, <1
 define <16 x bfloat> @vfmadd_vf_v16bf16(<16 x bfloat> %va, <16 x bfloat> %vb, bfloat %c) {
 ; CHECK-LABEL: vfmadd_vf_v16bf16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT:    vsetivli zero, 16, e16alt, m2, ta, ma
 ; CHECK-NEXT:    vfmadd.vf v8, fa0, v10
 ; CHECK-NEXT:    ret
   %head = insertelement <16 x bfloat> poison, bfloat %c, i32 0
@@ -117,7 +117,7 @@ define <16 x bfloat> @vfmadd_vf_v16bf16(<16 x bfloat> %va, <16 x bfloat> %vb, bf
 define <1 x bfloat> @vfmacc_vv_v1bf16(<1 x bfloat> %va, <1 x bfloat> %vb, <1 x bfloat> %vc) {
 ; CHECK-LABEL: vfmacc_vv_v1bf16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
+; CHECK-NEXT:    vsetivli zero, 1, e16alt, mf4, ta, ma
 ; CHECK-NEXT:    vfmacc.vv v8, v10, v9
 ; CHECK-NEXT:    ret
   %vd = call <1 x bfloat> @llvm.fma.v1bf16(<1 x bfloat> %vb, <1 x bfloat> %vc, <1 x bfloat> %va)
@@ -127,7 +127,7 @@ define <1 x bfloat> @vfmacc_vv_v1bf16(<1 x bfloat> %va, <1 x bfloat> %vb, <1 x b
 define <1 x bfloat> @vfmacc_vf_v1bf16(<1 x bfloat> %va, <1 x bfloat> %vb, bfloat %c) {
 ; CHECK-LABEL: vfmacc_vf_v1bf16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
+; CHECK-NEXT:    vsetivli zero, 1, e16alt, mf4, ta, ma
 ; CHECK-NEXT:    vfmacc.vf v8, fa0, v9
 ; CHECK-NEXT:    ret
   %head = insertelement <1 x bfloat> poison, bfloat %c, i32 0
@@ -139,7 +139,7 @@ define <1 x bfloat> @vfmacc_vf_v1bf16(<1 x bfloat> %va, <1 x bfloat> %vb, bfloat
 define <2 x bfloat> @vfmacc_vv_v2bf16(<2 x bfloat> %va, <2 x bfloat> %vb, <2 x bfloat> %vc) {
 ; CHECK-LABEL: vfmacc_vv_v2bf16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT:    vsetivli zero, 2, e16alt, mf4, ta, ma
 ; CHECK-NEXT:    vfmacc.vv v8, v10, v9
 ; CHECK-NEXT:    ret
   %vd = call <2 x bfloat> @llvm.fma.v2bf16(<2 x bfloat> %vb, <2 x bfloat> %vc, <2 x bfloat> %va)
@@ -149,7 +149,7 @@ define <2 x bfloat> @vfmacc_vv_v2bf16(<2 x bfloat> %va, <2 x bfloat> %vb, <2 x b
 define <2 x bfloat> @vfmacc_vf_v2bf16(<2 x bfloat> %va, <2 x bfloat> %vb, bfloat %c) {
 ; CHECK-LABEL: vfmacc_vf_v2bf16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT:    vsetivli zero, 2, e16alt, mf4, ta, ma
 ; CHECK-NEXT:    vfmacc.vf v8, fa0, v9
 ; CHECK-NEXT:    ret
   %head = insertelement <2 x bfloat> poison, bfloat %c, i32 0
@@ -161,7 +161,7 @@ define <2 x bfloat> @vfmacc_vf_v2bf16(<2 x bfloat> %va, <2 x bfloat> %vb, bfloat
 define <4 x bfloat> @vfmacc_vv_v4bf16(<4 x bfloat> %va, <4 x bfloat> %vb, <4 x bfloat> %vc) {
 ; CHECK-LABEL: vfmacc_vv_v4bf16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT:    vsetivli zero, 4, e16alt, mf2, ta, ma
 ; CHECK-NEXT:    vfmacc.vv v8, v10, v9
 ; CHECK-NEXT:    ret
   %vd = call <4 x bfloat> @llvm.fma.v4bf16(<4 x bfloat> %vb, <4 x bfloat> %vc, <4 x bfloat> %va)
@@ -171,7 +171,7 @@ define <4 x bfloat> @vfmacc_vv_v4bf16(<4 x bfloat> %va, <4 x bfloat> %vb, <4 x b
 define <4 x bfloat> @vfmacc_vf_v4bf16(<4 x bfloat> %va, <4 x bfloat> %vb, bfloat %c) {
 ; CHECK-LABEL: vfmacc_vf_v4bf16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT:    vsetivli zero, 4, e16alt, mf2, ta, ma
 ; CHECK-NEXT:    vfmacc.vf v8, fa0, v9
 ; CHECK-NEXT:    ret
   %head = insertelement <4 x bfloat> poison, bfloat %c, i32 0
@@ -183,7 +183,7 @@ define <4 x bfloat> @vfmacc_vf_v4bf16(<4 x bfloat> %va, <4 x bfloat> %vb, bfloat
 define <8 x bfloat> @vfmacc_vv_v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, <8 x bfloat> %vc) {
 ; CHECK-LABEL: vfmacc_vv_v8bf16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vsetivli zero, 8, e16alt, m1, ta, ma
 ; CHECK-NEXT:    vfmacc.vv v8, v10, v9
 ; CHECK-NEXT:    ret
   %vd = call <8 x bfloat> @llvm.fma.v8bf16(<8 x bfloat> %vb, <8 x bfloat> %vc, <8 x bfloat> %va)
@@ -193,7 +193,7 @@ define <8 x bfloat> @vfmacc_vv_v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, <8 x b
 define <8 x bfloat> @vfmacc_vf_v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, bfloat %c) {
 ; CHECK-LABEL: vfmacc_vf_v8bf16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vsetivli zero, 8, e16alt, m1, ta, ma
 ; CHECK-NEXT:    vfmacc.vf v8, fa0, v9
 ; CHECK-NEXT:    ret
   %head = insertelement <8 x bfloat> poison, bfloat %c, i32 0
@@ -205,7 +205,7 @@ define <8 x bfloat> @vfmacc_vf_v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, bfloat
 define <16 x bfloat> @vfmacc_vv_v16bf16(<16 x bfloat> %va, <16 x bfloat> %vb, <16 x bfloat> %vc) {
 ; CHECK-LABEL: vfmacc_vv_v16bf16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT:    vsetivli zero, 16, e16alt, m2, ta, ma
 ; CHECK-NEXT:    vfmacc.vv v8, v12, v10
 ; CHECK-NEXT:    ret
   %vd = call <16 x bfloat> @llvm.fma.v16bf16(<16 x bfloat> %vb, <16 x bfloat> %vc, <16 x bfloat> %va)
@@ -215,7 +215,7 @@ define <16 x bfloat> @vfmacc_vv_v16bf16(<16 x bfloat> %va, <16 x bfloat> %vb, <1
 define <16 x bfloat> @vfmacc_vf_v16bf16(<16 x bfloat> %va, <16 x bfloat> %vb, bfloat %c) {
 ; CHECK-LABEL: vfmacc_vf_v16bf16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT:    vsetivli zero, 16, e16alt, m2, ta, ma
 ; CHECK-NEXT:    vfmacc.vf v8, fa0, v10
 ; CHECK-NEXT:    ret
   %head = insertelement <16 x bfloat> poison, bfloat %c, i32 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsub-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsub-sdnode.ll
index d3f43c21f1638..c50c371d5e4ef 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsub-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsub-sdnode.ll
@@ -7,7 +7,7 @@
 define <1 x bfloat> @vfmsub_vv_v1bf16(<1 x bfloat> %va, <1 x bfloat> %vb, <1 x bfloat> %vc) {
 ; CHECK-LABEL: vfmsub_vv_v1bf16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
+; CHECK-NEXT:    vsetivli zero, 1, e16alt, mf4, ta, ma
 ; CHECK-NEXT:    vfmsub.vv v8, v9, v10
 ; CHECK-NEXT:    ret
   %neg = fneg <1 x bfloat> %vc
@@ -18,7 +18,7 @@ define <1 x bfloat> @vfmsub_vv_v1bf16(<1 x bfloat> %va, <1 x bfloat> %vb, <1 x b
 define <1 x bfloat> @vfmsub_vf_v1bf16(<1 x bfloat> %va, <1 x bfloat> %vb, bfloat %c) {
 ; CHECK-LABEL: vfmsub_vf_v1bf16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
+; CHECK-NEXT:    vsetivli zero, 1, e16alt, mf4, ta, ma
 ; CHECK-NEXT:    vfmsub.vf v8, fa0, v9
 ; CHECK-NEXT:    ret
   %head = insertelement <1 x bfloat> poison, bfloat %c, i32 0
@@ -31,7 +31,7 @@ define <1 x bfloat> @vfmsub_vf_v1bf16(<1 x bfloat> %va, <1 x bfloat> %vb, bfloat
 define <2 x bfloat> @vfmsub_vv_v2bf16(<2 x bfloat> %va, <2 x bfloat> %vb, <2 x bfloat> %vc) {
 ; CHECK-LABEL: vfmsub_vv_v2bf16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 2, e16,...
[truncated]

@4vtomat 4vtomat mentioned this pull request Jan 19, 2026
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topperc
topperc approved these changes Jan 19, 2026
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LGTM. This needs to be backported to 22.

@topperc topperc added this to the LLVM 22.x Release milestone Jan 19, 2026
@github-project-automation github-project-automation bot moved this to Needs Triage in LLVM Release Status Jan 19, 2026
@c-rhodes c-rhodes moved this from Needs Triage to Needs Fix in LLVM Release Status Jan 20, 2026
@4vtomat 4vtomat merged commit 3bab752 into llvm:main Jan 21, 2026
13 checks passed
@4vtomat 4vtomat deleted the zvfbfa_vfmadd_bug branch January 21, 2026 06:26
@github-project-automation github-project-automation bot moved this from Needs Fix to Done in LLVM Release Status Jan 21, 2026
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topperc commented Jan 21, 2026

/cherry-pick 3bab752

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4vtomat commented Jan 21, 2026

/cherry-pick 3bab752

Will this create a backport PR?

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llvmbot commented Jan 21, 2026

/pull-request #177101

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4vtomat commented Jan 21, 2026

/cherry-pick 3bab752

Will this create a backport PR?

Oh I saw it

4vtomat added a commit that referenced this pull request Jan 21, 2026
@4vtomat
[RISCV][llvm] Support strict fadd/fsub/fmul/fma codegen for zvfbfa (#…
d23c3a5 
…176719)

This is same as normal version.

stack on: #176716
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llvmbot commented Jan 21, 2026

Failed to cherry-pick: 3bab752

https://github.com/llvm/llvm-project/actions/runs/21199859602

Please manually backport the fix and push it to your github fork. Once this is done, please create a pull request

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llvmbot commented Jan 21, 2026

Failed to cherry-pick: 3bab752

https://github.com/llvm/llvm-project/actions/runs/21199869947

Please manually backport the fix and push it to your github fork. Once this is done, please create a pull request

llvm-sync bot pushed a commit to arm/arm-toolchain that referenced this pull request Jan 21, 2026
@4vtomat @github-actions
Automerge: [RISCV][llvm] Support strict fadd/fsub/fmul/fma codegen fo…
c939155 
…r zvfbfa (#176719)

This is same as normal version.

stack on: llvm/llvm-project#176716
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llvm-ci commented Jan 21, 2026

LLVM Buildbot has detected a new failure on builder sanitizer-aarch64-linux running on sanitizer-buildbot7 while building llvm at step 2 "annotate".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/51/builds/30484

Here is the relevant piece of the build log for the reference 
Step 2 (annotate) failure: 'python ../sanitizer_buildbot/sanitizers/zorg/buildbot/builders/sanitizers/buildbot_selector.py' (failure)
...
[201/205] Generating MSAN_INST_TEST_OBJECTS.msan_test.cpp.aarch64-with-call.o
[202/205] Generating Msan-aarch64-with-call-Test
[203/205] Generating MSAN_INST_TEST_OBJECTS.msan_test.cpp.aarch64.o
[204/205] Generating Msan-aarch64-Test
[204/205] Running compiler_rt regression tests
llvm-lit: /home/b/sanitizer-aarch64-linux/build/llvm-project/llvm/utils/lit/lit/discovery.py:273: warning: input '/home/b/sanitizer-aarch64-linux/build/build_default/runtimes/runtimes-bins/compiler-rt/test/interception/Unit' contained no tests
llvm-lit: /home/b/sanitizer-aarch64-linux/build/llvm-project/llvm/utils/lit/lit/discovery.py:273: warning: input '/home/b/sanitizer-aarch64-linux/build/build_default/runtimes/runtimes-bins/compiler-rt/test/sanitizer_common/Unit' contained no tests
llvm-lit: /home/b/sanitizer-aarch64-linux/build/llvm-project/llvm/utils/lit/lit/main.py:74: note: The test suite configuration requested an individual test timeout of 0 seconds but a timeout of 900 seconds was requested on the command line. Forcing timeout to be 900 seconds.
-- Testing: 3197 of 6342 tests, 72 workers --
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: XRay-aarch64-linux :: TestCases/Posix/basic-filtering.cpp (2471 of 3197)
******************** TEST 'XRay-aarch64-linux :: TestCases/Posix/basic-filtering.cpp' FAILED ********************
Exit Code: 1

Command Output (stdout):
--
# RUN: at line 4
/home/b/sanitizer-aarch64-linux/build/build_default/./bin/clang  --driver-mode=g++ -fxray-instrument   -Wthread-safety -Wthread-safety-reference -Wthread-safety-beta    -std=c++11 /home/b/sanitizer-aarch64-linux/build/llvm-project/compiler-rt/test/xray/TestCases/Posix/basic-filtering.cpp -o /home/b/sanitizer-aarch64-linux/build/build_default/runtimes/runtimes-bins/compiler-rt/test/xray/AARCH64LinuxConfig/TestCases/Posix/Output/basic-filtering.cpp.tmp -g
# executed command: /home/b/sanitizer-aarch64-linux/build/build_default/./bin/clang --driver-mode=g++ -fxray-instrument -Wthread-safety -Wthread-safety-reference -Wthread-safety-beta -std=c++11 /home/b/sanitizer-aarch64-linux/build/llvm-project/compiler-rt/test/xray/TestCases/Posix/basic-filtering.cpp -o /home/b/sanitizer-aarch64-linux/build/build_default/runtimes/runtimes-bins/compiler-rt/test/xray/AARCH64LinuxConfig/TestCases/Posix/Output/basic-filtering.cpp.tmp -g
# note: command had no output on stdout or stderr
# RUN: at line 5
rm -f basic-filtering-*
# executed command: rm -f 'basic-filtering-*'
# note: command had no output on stdout or stderr
# RUN: at line 6
env XRAY_OPTIONS="patch_premain=true xray_mode=xray-basic verbosity=1      xray_logfile_base=basic-filtering-      xray_naive_log_func_duration_threshold_us=1000      xray_naive_log_max_stack_depth=2"  /home/b/sanitizer-aarch64-linux/build/build_default/runtimes/runtimes-bins/compiler-rt/test/xray/AARCH64LinuxConfig/TestCases/Posix/Output/basic-filtering.cpp.tmp 2>&1 |      FileCheck /home/b/sanitizer-aarch64-linux/build/llvm-project/compiler-rt/test/xray/TestCases/Posix/basic-filtering.cpp
# executed command: env 'XRAY_OPTIONS=patch_premain=true xray_mode=xray-basic verbosity=1      xray_logfile_base=basic-filtering-      xray_naive_log_func_duration_threshold_us=1000      xray_naive_log_max_stack_depth=2' /home/b/sanitizer-aarch64-linux/build/build_default/runtimes/runtimes-bins/compiler-rt/test/xray/AARCH64LinuxConfig/TestCases/Posix/Output/basic-filtering.cpp.tmp
# note: command had no output on stdout or stderr
# executed command: FileCheck /home/b/sanitizer-aarch64-linux/build/llvm-project/compiler-rt/test/xray/TestCases/Posix/basic-filtering.cpp
# note: command had no output on stdout or stderr
# RUN: at line 11
ls basic-filtering-* | head -1 | tr -d '\n' > /home/b/sanitizer-aarch64-linux/build/build_default/runtimes/runtimes-bins/compiler-rt/test/xray/AARCH64LinuxConfig/TestCases/Posix/Output/basic-filtering.cpp.tmp.log
# executed command: ls 'basic-filtering-*'
# note: command had no output on stdout or stderr
# executed command: head -1
# note: command had no output on stdout or stderr
# executed command: tr -d '\n'
# note: command had no output on stdout or stderr
# RUN: at line 12
/home/b/sanitizer-aarch64-linux/build/build_default/./bin/llvm-xray convert --symbolize --output-format=yaml -instr_map=/home/b/sanitizer-aarch64-linux/build/build_default/runtimes/runtimes-bins/compiler-rt/test/xray/AARCH64LinuxConfig/TestCases/Posix/Output/basic-filtering.cpp.tmp      "/home/b/sanitizer-aarch64-linux/build/build_default/runtimes/runtimes-bins/compiler-rt/test/xray/AARCH64LinuxConfig/TestCases/Posix/basic-filtering-basic-filtering.cpp.tmp.1nZg4S" |      FileCheck /home/b/sanitizer-aarch64-linux/build/llvm-project/compiler-rt/test/xray/TestCases/Posix/basic-filtering.cpp --check-prefix TRACE
# executed command: /home/b/sanitizer-aarch64-linux/build/build_default/./bin/llvm-xray convert --symbolize --output-format=yaml -instr_map=/home/b/sanitizer-aarch64-linux/build/build_default/runtimes/runtimes-bins/compiler-rt/test/xray/AARCH64LinuxConfig/TestCases/Posix/Output/basic-filtering.cpp.tmp '%{readfile:/home/b/sanitizer-aarch64-linux/build/build_default/runtimes/runtimes-bins/compiler-rt/test/xray/AARCH64LinuxConfig/TestCases/Posix/Output/basic-filtering.cpp.tmp.log}'
# note: command had no output on stdout or stderr
# executed command: FileCheck /home/b/sanitizer-aarch64-linux/build/llvm-project/compiler-rt/test/xray/TestCases/Posix/basic-filtering.cpp --check-prefix TRACE
# .---command stderr------------
# | /home/b/sanitizer-aarch64-linux/build/llvm-project/compiler-rt/test/xray/TestCases/Posix/basic-filtering.cpp:61:15: error: TRACE-NOT: excluded string found in input
# | // TRACE-NOT: - { type: 0, func-id: {{.*}}, function: {{.*filtered.*}}, {{.*}} }
# |               ^
# | <stdin>:10:2: note: found here
# |  - { type: 0, func-id: 1, function: 'filtered()', cpu: 0, thread: 2017192, process: 2017192, kind: function-enter, tsc: 1768978017104777898, data: '' }
Step 11 (test compiler-rt debug) failure: test compiler-rt debug (failure)
...
[201/205] Generating MSAN_INST_TEST_OBJECTS.msan_test.cpp.aarch64-with-call.o
[202/205] Generating Msan-aarch64-with-call-Test
[203/205] Generating MSAN_INST_TEST_OBJECTS.msan_test.cpp.aarch64.o
[204/205] Generating Msan-aarch64-Test
[204/205] Running compiler_rt regression tests
llvm-lit: /home/b/sanitizer-aarch64-linux/build/llvm-project/llvm/utils/lit/lit/discovery.py:273: warning: input '/home/b/sanitizer-aarch64-linux/build/build_default/runtimes/runtimes-bins/compiler-rt/test/interception/Unit' contained no tests
llvm-lit: /home/b/sanitizer-aarch64-linux/build/llvm-project/llvm/utils/lit/lit/discovery.py:273: warning: input '/home/b/sanitizer-aarch64-linux/build/build_default/runtimes/runtimes-bins/compiler-rt/test/sanitizer_common/Unit' contained no tests
llvm-lit: /home/b/sanitizer-aarch64-linux/build/llvm-project/llvm/utils/lit/lit/main.py:74: note: The test suite configuration requested an individual test timeout of 0 seconds but a timeout of 900 seconds was requested on the command line. Forcing timeout to be 900 seconds.
-- Testing: 3197 of 6342 tests, 72 workers --
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: XRay-aarch64-linux :: TestCases/Posix/basic-filtering.cpp (2471 of 3197)
******************** TEST 'XRay-aarch64-linux :: TestCases/Posix/basic-filtering.cpp' FAILED ********************
Exit Code: 1

Command Output (stdout):
--
# RUN: at line 4
/home/b/sanitizer-aarch64-linux/build/build_default/./bin/clang  --driver-mode=g++ -fxray-instrument   -Wthread-safety -Wthread-safety-reference -Wthread-safety-beta    -std=c++11 /home/b/sanitizer-aarch64-linux/build/llvm-project/compiler-rt/test/xray/TestCases/Posix/basic-filtering.cpp -o /home/b/sanitizer-aarch64-linux/build/build_default/runtimes/runtimes-bins/compiler-rt/test/xray/AARCH64LinuxConfig/TestCases/Posix/Output/basic-filtering.cpp.tmp -g
# executed command: /home/b/sanitizer-aarch64-linux/build/build_default/./bin/clang --driver-mode=g++ -fxray-instrument -Wthread-safety -Wthread-safety-reference -Wthread-safety-beta -std=c++11 /home/b/sanitizer-aarch64-linux/build/llvm-project/compiler-rt/test/xray/TestCases/Posix/basic-filtering.cpp -o /home/b/sanitizer-aarch64-linux/build/build_default/runtimes/runtimes-bins/compiler-rt/test/xray/AARCH64LinuxConfig/TestCases/Posix/Output/basic-filtering.cpp.tmp -g
# note: command had no output on stdout or stderr
# RUN: at line 5
rm -f basic-filtering-*
# executed command: rm -f 'basic-filtering-*'
# note: command had no output on stdout or stderr
# RUN: at line 6
env XRAY_OPTIONS="patch_premain=true xray_mode=xray-basic verbosity=1      xray_logfile_base=basic-filtering-      xray_naive_log_func_duration_threshold_us=1000      xray_naive_log_max_stack_depth=2"  /home/b/sanitizer-aarch64-linux/build/build_default/runtimes/runtimes-bins/compiler-rt/test/xray/AARCH64LinuxConfig/TestCases/Posix/Output/basic-filtering.cpp.tmp 2>&1 |      FileCheck /home/b/sanitizer-aarch64-linux/build/llvm-project/compiler-rt/test/xray/TestCases/Posix/basic-filtering.cpp
# executed command: env 'XRAY_OPTIONS=patch_premain=true xray_mode=xray-basic verbosity=1      xray_logfile_base=basic-filtering-      xray_naive_log_func_duration_threshold_us=1000      xray_naive_log_max_stack_depth=2' /home/b/sanitizer-aarch64-linux/build/build_default/runtimes/runtimes-bins/compiler-rt/test/xray/AARCH64LinuxConfig/TestCases/Posix/Output/basic-filtering.cpp.tmp
# note: command had no output on stdout or stderr
# executed command: FileCheck /home/b/sanitizer-aarch64-linux/build/llvm-project/compiler-rt/test/xray/TestCases/Posix/basic-filtering.cpp
# note: command had no output on stdout or stderr
# RUN: at line 11
ls basic-filtering-* | head -1 | tr -d '\n' > /home/b/sanitizer-aarch64-linux/build/build_default/runtimes/runtimes-bins/compiler-rt/test/xray/AARCH64LinuxConfig/TestCases/Posix/Output/basic-filtering.cpp.tmp.log
# executed command: ls 'basic-filtering-*'
# note: command had no output on stdout or stderr
# executed command: head -1
# note: command had no output on stdout or stderr
# executed command: tr -d '\n'
# note: command had no output on stdout or stderr
# RUN: at line 12
/home/b/sanitizer-aarch64-linux/build/build_default/./bin/llvm-xray convert --symbolize --output-format=yaml -instr_map=/home/b/sanitizer-aarch64-linux/build/build_default/runtimes/runtimes-bins/compiler-rt/test/xray/AARCH64LinuxConfig/TestCases/Posix/Output/basic-filtering.cpp.tmp      "/home/b/sanitizer-aarch64-linux/build/build_default/runtimes/runtimes-bins/compiler-rt/test/xray/AARCH64LinuxConfig/TestCases/Posix/basic-filtering-basic-filtering.cpp.tmp.1nZg4S" |      FileCheck /home/b/sanitizer-aarch64-linux/build/llvm-project/compiler-rt/test/xray/TestCases/Posix/basic-filtering.cpp --check-prefix TRACE
# executed command: /home/b/sanitizer-aarch64-linux/build/build_default/./bin/llvm-xray convert --symbolize --output-format=yaml -instr_map=/home/b/sanitizer-aarch64-linux/build/build_default/runtimes/runtimes-bins/compiler-rt/test/xray/AARCH64LinuxConfig/TestCases/Posix/Output/basic-filtering.cpp.tmp '%{readfile:/home/b/sanitizer-aarch64-linux/build/build_default/runtimes/runtimes-bins/compiler-rt/test/xray/AARCH64LinuxConfig/TestCases/Posix/Output/basic-filtering.cpp.tmp.log}'
# note: command had no output on stdout or stderr
# executed command: FileCheck /home/b/sanitizer-aarch64-linux/build/llvm-project/compiler-rt/test/xray/TestCases/Posix/basic-filtering.cpp --check-prefix TRACE
# .---command stderr------------
# | /home/b/sanitizer-aarch64-linux/build/llvm-project/compiler-rt/test/xray/TestCases/Posix/basic-filtering.cpp:61:15: error: TRACE-NOT: excluded string found in input
# | // TRACE-NOT: - { type: 0, func-id: {{.*}}, function: {{.*filtered.*}}, {{.*}} }
# |               ^
# | <stdin>:10:2: note: found here
# |  - { type: 0, func-id: 1, function: 'filtered()', cpu: 0, thread: 2017192, process: 2017192, kind: function-enter, tsc: 1768978017104777898, data: '' }

c-rhodes pushed a commit to llvmbot/llvm-project that referenced this pull request Jan 21, 2026
@4vtomat @c-rhodes
[RISCV][llvm] Correct code generation of fma on zvfbfa (llvm#176716)
40f7eee 
Currently it's mapped to normal float16 instructions.

(cherry picked from commit 3bab752)
BStott6 pushed a commit to BStott6/llvm-project that referenced this pull request Jan 22, 2026
@4vtomat @BStott6
[RISCV][llvm] Correct code generation of fma on zvfbfa (llvm#176716)
ae07b80 
Currently it's mapped to normal float16 instructions.
BStott6 pushed a commit to BStott6/llvm-project that referenced this pull request Jan 22, 2026
@4vtomat @BStott6
[RISCV][llvm] Support strict fadd/fsub/fmul/fma codegen for zvfbfa (l…
8fe44bd 
…lvm#176719)

This is same as normal version.

stack on: llvm#176716
Harrish92 pushed a commit to Harrish92/llvm-project that referenced this pull request Jan 23, 2026
@4vtomat @Harrish92
[RISCV][llvm] Correct code generation of fma on zvfbfa (llvm#176716)
c986270 
Currently it's mapped to normal float16 instructions.
Harrish92 pushed a commit to Harrish92/llvm-project that referenced this pull request Jan 23, 2026
@4vtomat @Harrish92
[RISCV][llvm] Support strict fadd/fsub/fmul/fma codegen for zvfbfa (l…
bf3135a 
…lvm#176719)

This is same as normal version.

stack on: llvm#176716
Harrish92 pushed a commit to Harrish92/llvm-project that referenced this pull request Jan 24, 2026
@4vtomat @Harrish92
[RISCV][llvm] Correct code generation of fma on zvfbfa (llvm#176716)
730f7e8 
Currently it's mapped to normal float16 instructions.
Harrish92 pushed a commit to Harrish92/llvm-project that referenced this pull request Jan 24, 2026
@4vtomat @Harrish92
[RISCV][llvm] Support strict fadd/fsub/fmul/fma codegen for zvfbfa (l…
08f78ba 
…lvm#176719)

This is same as normal version.

stack on: llvm#176716
HugoSilvaSantos pushed a commit to HugoSilvaSantos/arm-toolchain that referenced this pull request Jan 27, 2026
@4vtomat @HugoSilvaSantos
[RISCV][llvm] Support strict fadd/fsub/fmul/fma codegen for zvfbfa (#…
a7b84d2 
…176719)

This is same as normal version.

stack on: llvm/llvm-project#176716
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@lukel97 lukel97 lukel97 approved these changes

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