[AMDGPU] Rewrite RegSeqNames using !foreach. NFC.#111994
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This reduces the total number of TableGen records produced by AMDGPU.td by about 6%.
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@llvm/pr-subscribers-backend-amdgpu Author: Jay Foad (jayfoad) ChangesThis reduces the total number of TableGen records produced by AMDGPU.td 1 Files Affected:
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
index ef9adde13348fe..3556f6a95b521e 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
@@ -88,15 +88,10 @@ class getSubRegs<int size> {
// Generates list of sequential register tuple names.
// E.g. RegSeq<3,2,2,"s">.ret -> [ "s[0:1]", "s[2:3]" ]
-class RegSeqNames<int last_reg, int stride, int size, string prefix,
- int start = 0> {
- int next = !add(start, stride);
- int end_reg = !add(start, size, -1);
- list<string> ret =
- !if(!le(end_reg, last_reg),
- !listconcat([prefix # "[" # start # ":" # end_reg # "]"],
- RegSeqNames<last_reg, stride, size, prefix, next>.ret),
- []);
+class RegSeqNames<int last_reg, int stride, int size, string prefix> {
+ defvar numtuples = !div(!sub(!add(last_reg, stride, 1), size), stride);
+ defvar range = !range(0, !mul(numtuples, stride), stride);
+ list<string> ret = !foreach(n, range, prefix # "[" # n # ":" # !add(n, size, -1) # "]");
}
// Generates list of dags for register tuples.
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arsenm
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Oct 11, 2024
ichaer
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Oct 11, 2024
…ent-indentonly * llvm-trunk/main: (6379 commits) [gn build] Port 1c94388 [RISCV] Introduce VLOptimizer pass (llvm#108640) [mlir][vector] Add more tests for ConvertVectorToLLVM (7/n) (llvm#111895) [libc++] Add output groups to run-buildbot (llvm#111739) [libc++abi] Remove unused LIBCXXABI_LIBCXX_INCLUDES CMake option (llvm#111824) [clang] Ignore inline namespace for `hasName` (llvm#109147) [AArch64] Disable consecutive store merging when Neon is unavailable (llvm#111519) [lldb] Fix finding make tool for tests (llvm#111980) Turn `-Wdeprecated-literal-operator` on by default (llvm#111027) [AMDGPU] Rewrite RegSeqNames using !foreach. NFC. (llvm#111994) Revert "Reland: [clang] Finish implementation of P0522 (llvm#111711)" Revert "[clang] CWG2398: improve overload resolution backwards compat (llvm#107350)" Revert "[clang] Implement TTP P0522 pack matching for deduced function template calls. (llvm#111457)" [Clang] Replace Intrinsic::getDeclaration with getOrInsertDeclaration (llvm#111990) Revert "[NVPTX] Prefer prmt.b32 over bfi.b32 (llvm#110766)" [RISCV] Add DAG combine to turn (sub (shl X, 8-Y), (shr X, Y)) into orc.b (llvm#111828) [libc] Fix compilation of new trig functions (llvm#111987) [NFC] Rename `Intrinsic::getDeclaration` to `getOrInsertDeclaration` (llvm#111752) [NFC][CodingStandard] Add additional example for if-else brace rule (llvm#111733) CodeGen: Remove redundant REQUIRES registered-target from tests (llvm#111982) ...
DanielCChen
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Oct 16, 2024
This reduces the total number of TableGen records produced by AMDGPU.td by about 6%.
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This reduces the total number of TableGen records produced by AMDGPU.td
by about 6%.