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[AMDGPU] Allow null operands in VImage tensor instructions (#200911)
NULL is equivalent to passing a block of SGPRs that are set to zero, and is allowed for 3+ opnds.
1 parent 383e5d2 commit de1ff3e

4 files changed

Lines changed: 23 additions & 14 deletions

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‎llvm/lib/Target/AMDGPU/MIMGInstructions.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2183,8 +2183,8 @@ class VIMAGE_TENSOR_Pseudo<string opName, bit _UpTo2D = 0> :
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bit UpTo2D = _UpTo2D;
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let InOperandList = !if(UpTo2D, (ins SReg_128_XNULL:$vaddr0, SReg_256_XNULL:$vaddr1, R128A16:$r128, CPol:$cpol),
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(ins SReg_128_XNULL:$vaddr0, SReg_256_XNULL:$vaddr1, SReg_128_XNULL:$vaddr2,
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SReg_128_XNULL:$vaddr3, R128A16:$r128, CPol:$cpol));
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(ins SReg_128_XNULL:$vaddr0, SReg_256_XNULL:$vaddr1, SReg_128:$vaddr2,
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SReg_128:$vaddr3, R128A16:$r128, CPol:$cpol));
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string AsmOperands = " $vaddr0, $vaddr1"#!if(UpTo2D, "", ", $vaddr2, $vaddr3")#"$r128$cpol";
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}
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‎llvm/test/MC/AMDGPU/gfx1250_asm_vimage.s‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,18 @@ tensor_store_from_lds s[0:3], s[4:11] th:TH_STORE_BYPASS scope:SCOPE_SYS
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// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU (gfx1200): tensor_store_from_lds
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// GFX1250: tensor_store_from_lds s[0:3], s[4:11] th:TH_STORE_BYPASS scope:SCOPE_SYS ; encoding: [0x01,0x40,0x71,0xd0,0x00,0x00,0x3c,0x7c,0x00,0x04,0x7c,0x7c]
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tensor_store_from_lds s[0:3], s[4:11], null, null th:TH_STORE_NT_HT scope:SCOPE_DEV
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// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU (gfx1200): tensor_store_from_lds
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// GFX1250: tensor_store_from_lds s[0:3], s[4:11], null, null th:TH_STORE_NT_HT scope:SCOPE_DEV ; encoding: [0x01,0x40,0x71,0xd0,0x00,0x00,0x68,0x7c,0x00,0x04,0x7c,0x7c]
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tensor_store_from_lds s[0:3], s[4:11], null, s[16:19] th:TH_STORE_NT_HT scope:SCOPE_DEV
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// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU (gfx1200): tensor_store_from_lds
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// GFX1250: tensor_store_from_lds s[0:3], s[4:11], null, s[16:19] th:TH_STORE_NT_HT scope:SCOPE_DEV ; encoding: [0x01,0x40,0x71,0xd0,0x00,0x00,0x68,0x7c,0x00,0x04,0x7c,0x10]
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tensor_store_from_lds s[0:3], s[4:11], s[12:15], null th:TH_STORE_NT_HT scope:SCOPE_DEV
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// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU (gfx1200): tensor_store_from_lds
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// GFX1250: tensor_store_from_lds s[0:3], s[4:11], s[12:15], null th:TH_STORE_NT_HT scope:SCOPE_DEV ; encoding: [0x01,0x40,0x71,0xd0,0x00,0x00,0x68,0x7c,0x00,0x04,0x0c,0x7c]
40+
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tensor_store_from_lds s[0:3], s[4:11], s[12:15], s[16:19]
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// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU (gfx1200): tensor_store_from_lds
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// GFX1250: tensor_store_from_lds s[0:3], s[4:11], s[12:15], s[16:19] ; encoding: [0x01,0x40,0x71,0xd0,0x00,0x00,0x00,0x7c,0x00,0x04,0x0c,0x10]

‎llvm/test/MC/AMDGPU/gfx1250_asm_vimage_err.s‎

Lines changed: 0 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -37,12 +37,6 @@ tensor_load_to_lds null, s[4:11], s[12:15], s[16:19]
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tensor_load_to_lds s[0:3], null, s[12:15], s[16:19]
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// GFX1250-ERR: :[[@LINE-1]]:28: error: invalid operand for instruction
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tensor_load_to_lds s[0:3], s[4:11], null, s[16:19]
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// GFX1250-ERR: :[[@LINE-1]]:37: error: invalid operand for instruction
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tensor_load_to_lds s[0:3], s[4:11], s[12:15], null
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// GFX1250-ERR: :[[@LINE-1]]:47: error: invalid operand for instruction
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tensor_store_from_lds null, s[4:11]
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// GFX1250-ERR: :[[@LINE-1]]:23: error: invalid operand for instruction
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@@ -55,12 +49,6 @@ tensor_store_from_lds null, s[4:11], s[12:15], s[16:19]
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tensor_store_from_lds s[0:3], null, s[12:15], s[16:19]
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// GFX1250-ERR: :[[@LINE-1]]:31: error: invalid operand for instruction
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tensor_store_from_lds s[0:3], s[4:11], null, s[16:19]
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// GFX1250-ERR: :[[@LINE-1]]:40: error: invalid operand for instruction
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tensor_store_from_lds s[0:3], s[4:11], s[12:15], null
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// GFX1250-ERR: :[[@LINE-1]]:50: error: invalid operand for instruction
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tensor_load_to_lds s[14:17], s[4:11]
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// GFX1250-ERR: :[[@LINE-1]]:20: error: invalid register alignment
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‎llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vimage.txt‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,15 @@
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0x01,0x40,0x71,0xd0,0x00,0x00,0x3c,0x7c,0x00,0x04,0x7c,0x7c
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# GFX1250: tensor_store_from_lds s[0:3], s[4:11] th:TH_STORE_BYPASS scope:SCOPE_SYS ; encoding: [0x01,0x40,0x71,0xd0,0x00,0x00,0x3c,0x7c,0x00,0x04,0x7c,0x7c]
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0x01,0x40,0x71,0xd0,0x00,0x00,0x68,0x7c,0x00,0x04,0x7c,0x7c
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# GFX1250: tensor_store_from_lds s[0:3], s[4:11] th:TH_STORE_NT_HT scope:SCOPE_DEV ; encoding: [0x01,0x40,0x71,0xd0,0x00,0x00,0x68,0x7c,0x00,0x04,0x7c,0x7c]
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0x01,0x40,0x71,0xd0,0x00,0x00,0x68,0x7c,0x00,0x04,0x7c,0x10
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# GFX1250: tensor_store_from_lds s[0:3], s[4:11], null, s[16:19] th:TH_STORE_NT_HT scope:SCOPE_DEV ; encoding: [0x01,0x40,0x71,0xd0,0x00,0x00,0x68,0x7c,0x00,0x04,0x7c,0x10]
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0x01,0x40,0x71,0xd0,0x00,0x00,0x68,0x7c,0x00,0x04,0x0c,0x7c
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# GFX1250: tensor_store_from_lds s[0:3], s[4:11], s[12:15], null th:TH_STORE_NT_HT scope:SCOPE_DEV ; encoding: [0x01,0x40,0x71,0xd0,0x00,0x00,0x68,0x7c,0x00,0x04,0x0c,0x7c]
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0x01,0x40,0x71,0xd0,0x00,0x00,0x00,0x7c,0x00,0x04,0x0c,0x10
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# GFX1250: tensor_store_from_lds s[0:3], s[4:11], s[12:15], s[16:19] ; encoding: [0x01,0x40,0x71,0xd0,0x00,0x00,0x00,0x7c,0x00,0x04,0x0c,0x10]
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