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[RISCV][P-ext] Support v4i16/v2i32->v4i8/v2i16 truncate. (#201757)
1 parent 05d4fd0 commit d4ec02e

5 files changed

Lines changed: 27 additions & 62 deletions

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‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -655,6 +655,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
655655
setOperationAction(ISD::MUL, {MVT::v4i16, MVT::v8i8}, Custom);
656656
setOperationAction({ISD::SIGN_EXTEND, ISD::ZERO_EXTEND},
657657
{MVT::v4i16, MVT::v2i32}, Legal);
658+
setOperationAction(ISD::TRUNCATE, {MVT::v4i8, MVT::v2i16}, Legal);
658659
setOperationAction(ISD::SETCC, P64VecVTs, Legal);
659660
setCondCodeAction(
660661
{ISD::SETGE, ISD::SETUGT, ISD::SETUGE, ISD::SETULE, ISD::SETLE},

‎llvm/lib/Target/RISCV/RISCVInstrInfoP.td‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2206,6 +2206,11 @@ let append Predicates = [IsRV32] in {
22062206
def : Pat<(v2i16 (build_vector (XLenVT GPR:$a), (XLenVT GPR:$b))),
22072207
(PACK GPR:$a, GPR:$b)>;
22082208

2209+
// Truncate patterns using pnsrli.
2210+
// FIXME: Support general shift+trunc
2211+
def : Pat<(v4i8 (trunc (v4i16 GPRPair:$rs))), (PNSRLI_B GPRPair:$rs, 0)>;
2212+
def : Pat<(v2i16 (trunc (v2i32 GPRPair:$rs))), (PNSRLI_H GPRPair:$rs, 0)>;
2213+
22092214
// Basic 8-bit arithmetic patterns
22102215
def : PatGprPairGprPair<add, PADD_DB, v8i8>;
22112216
def : PatGprPairGprPair<sub, PSUB_DB, v8i8>;

‎llvm/test/CodeGen/RISCV/rvp-narrowing-shift-trunc.ll‎

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@ define i32 @trunc_lshr_v2i32_to_v2i16(i64 %a.coerce) {
1313
; CHECK-RV32-LABEL: trunc_lshr_v2i32_to_v2i16:
1414
; CHECK-RV32: # %bb.0:
1515
; CHECK-RV32-NEXT: psrli.dw a0, a0, 8
16-
; CHECK-RV32-NEXT: pack a0, a0, a1
16+
; CHECK-RV32-NEXT: pncvt.h a0, a0
1717
; CHECK-RV32-NEXT: ret
1818
;
1919
; CHECK-RV64-LABEL: trunc_lshr_v2i32_to_v2i16:
@@ -33,7 +33,7 @@ define i32 @trunc_ashr_v2i32_to_v2i16(i64 %a.coerce) {
3333
; CHECK-RV32-LABEL: trunc_ashr_v2i32_to_v2i16:
3434
; CHECK-RV32: # %bb.0:
3535
; CHECK-RV32-NEXT: psrli.dw a0, a0, 8
36-
; CHECK-RV32-NEXT: pack a0, a0, a1
36+
; CHECK-RV32-NEXT: pncvt.h a0, a0
3737
; CHECK-RV32-NEXT: ret
3838
;
3939
; CHECK-RV64-LABEL: trunc_ashr_v2i32_to_v2i16:
@@ -53,10 +53,7 @@ define i32 @trunc_lshr_v4i16_to_v4i8(i64 %a.coerce) {
5353
; CHECK-RV32-LABEL: trunc_lshr_v4i16_to_v4i8:
5454
; CHECK-RV32: # %bb.0:
5555
; CHECK-RV32-NEXT: psrli.dh a0, a0, 4
56-
; CHECK-RV32-NEXT: srli a3, a1, 16
57-
; CHECK-RV32-NEXT: srli a2, a0, 16
58-
; CHECK-RV32-NEXT: ppaire.db a0, a0, a2
59-
; CHECK-RV32-NEXT: pack a0, a0, a1
56+
; CHECK-RV32-NEXT: pncvt.b a0, a0
6057
; CHECK-RV32-NEXT: ret
6158
;
6259
; CHECK-RV64-LABEL: trunc_lshr_v4i16_to_v4i8:

‎llvm/test/CodeGen/RISCV/rvp-simd-32.ll‎

Lines changed: 2 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1306,10 +1306,7 @@ define <4 x i8> @test_pmulhsu_b(<4 x i8> %a, <4 x i8> %b) {
13061306
; RV32-NEXT: pwmul.h a2, a2, a0
13071307
; RV32-NEXT: pncvt.h a0, a2
13081308
; RV32-NEXT: psrli.dh a0, a0, 8
1309-
; RV32-NEXT: srli a3, a1, 16
1310-
; RV32-NEXT: srli a2, a0, 16
1311-
; RV32-NEXT: ppaire.db a0, a0, a2
1312-
; RV32-NEXT: pack a0, a0, a1
1309+
; RV32-NEXT: pncvt.b a0, a0
13131310
; RV32-NEXT: ret
13141311
;
13151312
; RV64-LABEL: test_pmulhsu_b:
@@ -1347,10 +1344,7 @@ define <4 x i8> @test_pmulhsu_b_commuted(<4 x i8> %a, <4 x i8> %b) {
13471344
; RV32-NEXT: pwmul.h a2, a2, a0
13481345
; RV32-NEXT: pncvt.h a0, a2
13491346
; RV32-NEXT: psrli.dh a0, a0, 8
1350-
; RV32-NEXT: srli a3, a1, 16
1351-
; RV32-NEXT: srli a2, a0, 16
1352-
; RV32-NEXT: ppaire.db a0, a0, a2
1353-
; RV32-NEXT: pack a0, a0, a1
1347+
; RV32-NEXT: pncvt.b a0, a0
13541348
; RV32-NEXT: ret
13551349
;
13561350
; RV64-LABEL: test_pmulhsu_b_commuted:

‎llvm/test/CodeGen/RISCV/rvp-simd-64.ll‎

Lines changed: 16 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -2312,18 +2312,10 @@ define <8 x i8> @test_pmulh_b(<8 x i8> %a, <8 x i8> %b) {
23122312
; RV32-NEXT: pncvt.h a3, a2
23132313
; RV32-NEXT: pncvt.h a6, a0
23142314
; RV32-NEXT: pncvt.h a2, a4
2315-
; RV32-NEXT: psrli.dh a0, a2, 8
2316-
; RV32-NEXT: psrli.dh a2, a6, 8
2317-
; RV32-NEXT: srli a4, a3, 16
2318-
; RV32-NEXT: srli a5, a2, 16
2319-
; RV32-NEXT: srli a6, a1, 16
2320-
; RV32-NEXT: srli a7, a0, 16
2321-
; RV32-NEXT: ppaire.b a3, a3, a4
2322-
; RV32-NEXT: ppaire.b a2, a2, a5
2323-
; RV32-NEXT: ppaire.b a4, a1, a6
2324-
; RV32-NEXT: ppaire.b a0, a0, a7
2325-
; RV32-NEXT: pack a1, a2, a3
2326-
; RV32-NEXT: pack a0, a0, a4
2315+
; RV32-NEXT: psrli.dh a2, a2, 8
2316+
; RV32-NEXT: psrli.dh a0, a6, 8
2317+
; RV32-NEXT: pncvt.b a1, a0
2318+
; RV32-NEXT: pncvt.b a0, a2
23272319
; RV32-NEXT: ret
23282320
;
23292321
; RV64-LABEL: test_pmulh_b:
@@ -2394,18 +2386,10 @@ define <8 x i8> @test_pmulhu_b(<8 x i8> %a, <8 x i8> %b) {
23942386
; RV32-NEXT: pncvt.h a3, a2
23952387
; RV32-NEXT: pncvt.h a6, a0
23962388
; RV32-NEXT: pncvt.h a2, a4
2397-
; RV32-NEXT: psrli.dh a0, a2, 8
2398-
; RV32-NEXT: psrli.dh a2, a6, 8
2399-
; RV32-NEXT: srli a4, a3, 16
2400-
; RV32-NEXT: srli a5, a2, 16
2401-
; RV32-NEXT: srli a6, a1, 16
2402-
; RV32-NEXT: srli a7, a0, 16
2403-
; RV32-NEXT: ppaire.b a3, a3, a4
2404-
; RV32-NEXT: ppaire.b a2, a2, a5
2405-
; RV32-NEXT: ppaire.b a4, a1, a6
2406-
; RV32-NEXT: ppaire.b a0, a0, a7
2407-
; RV32-NEXT: pack a1, a2, a3
2408-
; RV32-NEXT: pack a0, a0, a4
2389+
; RV32-NEXT: psrli.dh a2, a2, 8
2390+
; RV32-NEXT: psrli.dh a0, a6, 8
2391+
; RV32-NEXT: pncvt.b a1, a0
2392+
; RV32-NEXT: pncvt.b a0, a2
24092393
; RV32-NEXT: ret
24102394
;
24112395
; RV64-LABEL: test_pmulhu_b:
@@ -2475,18 +2459,10 @@ define <8 x i8> @test_pmulhsu_b(<8 x i8> %a, <8 x i8> %b) {
24752459
; RV32-NEXT: pncvt.h a3, a2
24762460
; RV32-NEXT: pncvt.h a6, a0
24772461
; RV32-NEXT: pncvt.h a2, a4
2478-
; RV32-NEXT: psrli.dh a0, a2, 8
2479-
; RV32-NEXT: psrli.dh a2, a6, 8
2480-
; RV32-NEXT: srli a4, a3, 16
2481-
; RV32-NEXT: srli a5, a2, 16
2482-
; RV32-NEXT: srli a6, a1, 16
2483-
; RV32-NEXT: srli a7, a0, 16
2484-
; RV32-NEXT: ppaire.b a3, a3, a4
2485-
; RV32-NEXT: ppaire.b a2, a2, a5
2486-
; RV32-NEXT: ppaire.b a4, a1, a6
2487-
; RV32-NEXT: ppaire.b a0, a0, a7
2488-
; RV32-NEXT: pack a1, a2, a3
2489-
; RV32-NEXT: pack a0, a0, a4
2462+
; RV32-NEXT: psrli.dh a2, a2, 8
2463+
; RV32-NEXT: psrli.dh a0, a6, 8
2464+
; RV32-NEXT: pncvt.b a1, a0
2465+
; RV32-NEXT: pncvt.b a0, a2
24902466
; RV32-NEXT: ret
24912467
;
24922468
; RV64-LABEL: test_pmulhsu_b:
@@ -2558,18 +2534,10 @@ define <8 x i8> @test_pmulhsu_b_commuted(<8 x i8> %a, <8 x i8> %b) {
25582534
; RV32-NEXT: pncvt.h a3, a2
25592535
; RV32-NEXT: pncvt.h a6, a0
25602536
; RV32-NEXT: pncvt.h a2, a4
2561-
; RV32-NEXT: psrli.dh a0, a2, 8
2562-
; RV32-NEXT: psrli.dh a2, a6, 8
2563-
; RV32-NEXT: srli a4, a3, 16
2564-
; RV32-NEXT: srli a5, a2, 16
2565-
; RV32-NEXT: srli a6, a1, 16
2566-
; RV32-NEXT: srli a7, a0, 16
2567-
; RV32-NEXT: ppaire.b a3, a3, a4
2568-
; RV32-NEXT: ppaire.b a2, a2, a5
2569-
; RV32-NEXT: ppaire.b a4, a1, a6
2570-
; RV32-NEXT: ppaire.b a0, a0, a7
2571-
; RV32-NEXT: pack a1, a2, a3
2572-
; RV32-NEXT: pack a0, a0, a4
2537+
; RV32-NEXT: psrli.dh a2, a2, 8
2538+
; RV32-NEXT: psrli.dh a0, a6, 8
2539+
; RV32-NEXT: pncvt.b a1, a0
2540+
; RV32-NEXT: pncvt.b a0, a2
25732541
; RV32-NEXT: ret
25742542
;
25752543
; RV64-LABEL: test_pmulhsu_b_commuted:

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