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[SPARC] Set how many bytes load from or store to stack slot (#182674)
Refer from: https://reviews.llvm.org/D44782 The testcase is copied from llvm/test/CodeGen/RISCV/stack-slot-coloring.mir. (cherry picked from commit 1548723)
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3 files changed

+233
-22
lines changed

3 files changed

+233
-22
lines changed

‎llvm/lib/Target/Sparc/SparcInstrInfo.cpp‎

Lines changed: 50 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -47,15 +47,31 @@ SparcInstrInfo::SparcInstrInfo(const SparcSubtarget &ST)
4747
/// not, return 0. This predicate must return 0 if the instruction has
4848
/// any side effects other than loading from the stack slot.
4949
Register SparcInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
50-
int &FrameIndex) const {
51-
if (MI.getOpcode() == SP::LDri || MI.getOpcode() == SP::LDXri ||
52-
MI.getOpcode() == SP::LDFri || MI.getOpcode() == SP::LDDFri ||
53-
MI.getOpcode() == SP::LDQFri) {
54-
if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
55-
MI.getOperand(2).getImm() == 0) {
56-
FrameIndex = MI.getOperand(1).getIndex();
57-
return MI.getOperand(0).getReg();
58-
}
50+
int &FrameIndex,
51+
TypeSize &MemBytes) const {
52+
switch (MI.getOpcode()) {
53+
default:
54+
return 0;
55+
case SP::LDri:
56+
MemBytes = TypeSize::getFixed(4);
57+
break;
58+
case SP::LDXri:
59+
MemBytes = TypeSize::getFixed(8);
60+
break;
61+
case SP::LDFri:
62+
MemBytes = TypeSize::getFixed(4);
63+
break;
64+
case SP::LDDFri:
65+
MemBytes = TypeSize::getFixed(8);
66+
break;
67+
case SP::LDQFri:
68+
MemBytes = TypeSize::getFixed(16);
69+
break;
70+
}
71+
if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
72+
MI.getOperand(2).getImm() == 0) {
73+
FrameIndex = MI.getOperand(1).getIndex();
74+
return MI.getOperand(0).getReg();
5975
}
6076
return 0;
6177
}
@@ -66,15 +82,31 @@ Register SparcInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
6682
/// not, return 0. This predicate must return 0 if the instruction has
6783
/// any side effects other than storing to the stack slot.
6884
Register SparcInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
69-
int &FrameIndex) const {
70-
if (MI.getOpcode() == SP::STri || MI.getOpcode() == SP::STXri ||
71-
MI.getOpcode() == SP::STFri || MI.getOpcode() == SP::STDFri ||
72-
MI.getOpcode() == SP::STQFri) {
73-
if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
74-
MI.getOperand(1).getImm() == 0) {
75-
FrameIndex = MI.getOperand(0).getIndex();
76-
return MI.getOperand(2).getReg();
77-
}
85+
int &FrameIndex,
86+
TypeSize &MemBytes) const {
87+
switch (MI.getOpcode()) {
88+
default:
89+
return 0;
90+
case SP::STri:
91+
MemBytes = TypeSize::getFixed(4);
92+
break;
93+
case SP::STXri:
94+
MemBytes = TypeSize::getFixed(8);
95+
break;
96+
case SP::STFri:
97+
MemBytes = TypeSize::getFixed(4);
98+
break;
99+
case SP::STDFri:
100+
MemBytes = TypeSize::getFixed(8);
101+
break;
102+
case SP::STQFri:
103+
MemBytes = TypeSize::getFixed(16);
104+
break;
105+
}
106+
if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
107+
MI.getOperand(1).getImm() == 0) {
108+
FrameIndex = MI.getOperand(0).getIndex();
109+
return MI.getOperand(2).getReg();
78110
}
79111
return 0;
80112
}

‎llvm/lib/Target/Sparc/SparcInstrInfo.h‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -53,16 +53,16 @@ class SparcInstrInfo : public SparcGenInstrInfo {
5353
/// the destination along with the FrameIndex of the loaded stack slot. If
5454
/// not, return 0. This predicate must return 0 if the instruction has
5555
/// any side effects other than loading from the stack slot.
56-
Register isLoadFromStackSlot(const MachineInstr &MI,
57-
int &FrameIndex) const override;
56+
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex,
57+
TypeSize &MemBytes) const override;
5858

5959
/// isStoreToStackSlot - If the specified machine instruction is a direct
6060
/// store to a stack slot, return the virtual or physical register number of
6161
/// the source reg along with the FrameIndex of the loaded stack slot. If
6262
/// not, return 0. This predicate must return 0 if the instruction has
6363
/// any side effects other than storing to the stack slot.
64-
Register isStoreToStackSlot(const MachineInstr &MI,
65-
int &FrameIndex) const override;
64+
Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex,
65+
TypeSize &MemBytes) const override;
6666

6767
MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
6868

‎llvm/test/CodeGen/SPARC/stack-slot-coloring.mir‎

Lines changed: 179 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,179 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
2+
# RUN: llc -mtriple=sparcv9 -run-pass=greedy,virtregrewriter,stack-slot-coloring %s -o - | FileCheck %s
3+
# RUN: llc -mtriple=sparc -run-pass=greedy,virtregrewriter,stack-slot-coloring %s -o - | FileCheck %s
4+
5+
--- |
6+
define dso_local i32 @main() local_unnamed_addr {
7+
entry:
8+
%a = alloca i64, align 4
9+
ret i32 0
10+
}
11+
...
12+
---
13+
name: main
14+
stack:
15+
- { id: 0, name: a, type: spill-slot, offset: 0, size: 8, alignment: 4,
16+
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
17+
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
18+
body: |
19+
bb.0.entry:
20+
; CHECK-LABEL: name: main
21+
; CHECK: $i0 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
22+
; CHECK-NEXT: $i1 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
23+
; CHECK-NEXT: $i3 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
24+
; CHECK-NEXT: $i4 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
25+
; CHECK-NEXT: $i5 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
26+
; CHECK-NEXT: $i6 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
27+
; CHECK-NEXT: $i7 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
28+
; CHECK-NEXT: $g0 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
29+
; CHECK-NEXT: $g1 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
30+
; CHECK-NEXT: $g2 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
31+
; CHECK-NEXT: $g3 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
32+
; CHECK-NEXT: $g4 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
33+
; CHECK-NEXT: $g5 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
34+
; CHECK-NEXT: $g6 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
35+
; CHECK-NEXT: $g7 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
36+
; CHECK-NEXT: $l0 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
37+
; CHECK-NEXT: $l1 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
38+
; CHECK-NEXT: $l2 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
39+
; CHECK-NEXT: $l3 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
40+
; CHECK-NEXT: $l4 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
41+
; CHECK-NEXT: $l5 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
42+
; CHECK-NEXT: $l6 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
43+
; CHECK-NEXT: $l7 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
44+
; CHECK-NEXT: $o0 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
45+
; CHECK-NEXT: $o1 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
46+
; CHECK-NEXT: $o2 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
47+
; CHECK-NEXT: $o3 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
48+
; CHECK-NEXT: $o4 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
49+
; CHECK-NEXT: $o5 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
50+
; CHECK-NEXT: $o6 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
51+
; CHECK-NEXT: $o7 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
52+
; CHECK-NEXT: renamable $i2 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
53+
; CHECK-NEXT: STXri %stack.1, 0, killed renamable $i2 :: (store (s64) into %stack.1)
54+
; CHECK-NEXT: renamable $i2 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
55+
; CHECK-NEXT: STXri %stack.0.a, 0, killed renamable $i2 :: (store (s64) into %ir.a)
56+
; CHECK-NEXT: renamable $i2 = LDXri %stack.1, 0 :: (load (s64) from %stack.1)
57+
; CHECK-NEXT: STri %stack.0.a, 0, killed renamable $i2 :: (store (s32) into %ir.a)
58+
; CHECK-NEXT: renamable $i2 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
59+
; CHECK-NEXT: STXri %stack.1, 0, killed renamable $i2 :: (store (s64) into %stack.1)
60+
; CHECK-NEXT: renamable $i2 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
61+
; CHECK-NEXT: STXri %stack.0.a, 0, killed renamable $i2 :: (store (s64) into %ir.a)
62+
; CHECK-NEXT: renamable $i2 = LDXri %stack.1, 0 :: (load (s64) from %stack.1)
63+
; CHECK-NEXT: STri %stack.0.a, 0, killed renamable $i2 :: (store (s32) into %ir.a)
64+
; CHECK-NEXT: STri %stack.0.a, 0, $i0 :: (store (s32) into %ir.a)
65+
; CHECK-NEXT: STri %stack.0.a, 0, $i1 :: (store (s32) into %ir.a)
66+
; CHECK-NEXT: STri %stack.0.a, 0, $i3 :: (store (s32) into %ir.a)
67+
; CHECK-NEXT: STri %stack.0.a, 0, $i4 :: (store (s32) into %ir.a)
68+
; CHECK-NEXT: STri %stack.0.a, 0, $i5 :: (store (s32) into %ir.a)
69+
; CHECK-NEXT: STri %stack.0.a, 0, $i6 :: (store (s32) into %ir.a)
70+
; CHECK-NEXT: STri %stack.0.a, 0, $i7 :: (store (s32) into %ir.a)
71+
; CHECK-NEXT: STri %stack.0.a, 0, $g0 :: (store (s32) into %ir.a)
72+
; CHECK-NEXT: STri %stack.0.a, 0, $g1 :: (store (s32) into %ir.a)
73+
; CHECK-NEXT: STri %stack.0.a, 0, $g2 :: (store (s32) into %ir.a)
74+
; CHECK-NEXT: STri %stack.0.a, 0, $g3 :: (store (s32) into %ir.a)
75+
; CHECK-NEXT: STri %stack.0.a, 0, $g4 :: (store (s32) into %ir.a)
76+
; CHECK-NEXT: STri %stack.0.a, 0, $g5 :: (store (s32) into %ir.a)
77+
; CHECK-NEXT: STri %stack.0.a, 0, $g6 :: (store (s32) into %ir.a)
78+
; CHECK-NEXT: STri %stack.0.a, 0, $g7 :: (store (s32) into %ir.a)
79+
; CHECK-NEXT: STri %stack.0.a, 0, $l0 :: (store (s32) into %ir.a)
80+
; CHECK-NEXT: STri %stack.0.a, 0, $l1 :: (store (s32) into %ir.a)
81+
; CHECK-NEXT: STri %stack.0.a, 0, $l2 :: (store (s32) into %ir.a)
82+
; CHECK-NEXT: STri %stack.0.a, 0, $l3 :: (store (s32) into %ir.a)
83+
; CHECK-NEXT: STri %stack.0.a, 0, $l4 :: (store (s32) into %ir.a)
84+
; CHECK-NEXT: STri %stack.0.a, 0, $l5 :: (store (s32) into %ir.a)
85+
; CHECK-NEXT: STri %stack.0.a, 0, $l6 :: (store (s32) into %ir.a)
86+
; CHECK-NEXT: STri %stack.0.a, 0, $l7 :: (store (s32) into %ir.a)
87+
; CHECK-NEXT: STri %stack.0.a, 0, $o0 :: (store (s32) into %ir.a)
88+
; CHECK-NEXT: STri %stack.0.a, 0, $o1 :: (store (s32) into %ir.a)
89+
; CHECK-NEXT: STri %stack.0.a, 0, $o2 :: (store (s32) into %ir.a)
90+
; CHECK-NEXT: STri %stack.0.a, 0, $o3 :: (store (s32) into %ir.a)
91+
; CHECK-NEXT: STri %stack.0.a, 0, $o4 :: (store (s32) into %ir.a)
92+
; CHECK-NEXT: STri %stack.0.a, 0, $o5 :: (store (s32) into %ir.a)
93+
; CHECK-NEXT: STri %stack.0.a, 0, $o6 :: (store (s32) into %ir.a)
94+
; CHECK-NEXT: STri %stack.0.a, 0, $o7 :: (store (s32) into %ir.a)
95+
; CHECK-NEXT: RETL 8, implicit $i0
96+
$i0 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
97+
$i1 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
98+
$i3 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
99+
$i4 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
100+
$i5 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
101+
$i6 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
102+
$i7 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
103+
$g0 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
104+
$g1 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
105+
$g2 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
106+
$g3 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
107+
$g4 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
108+
$g5 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
109+
$g6 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
110+
$g7 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
111+
$l0 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
112+
$l1 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
113+
$l2 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
114+
$l3 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
115+
$l4 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
116+
$l5 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
117+
$l6 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
118+
$l7 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
119+
$o0 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
120+
$o1 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
121+
$o2 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
122+
$o3 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
123+
$o4 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
124+
$o5 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
125+
$o6 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
126+
$o7 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
127+
128+
; First vreg load
129+
%1:i64regs = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
130+
131+
; First faulty sequence; %1 spilt
132+
%12:i64regs = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
133+
STXri %stack.0.a, 0, %12 :: (store (s64) into %ir.a)
134+
135+
; Store %1 to avoid it being optimised out, will result in a load-from-spill
136+
STri %stack.0.a, 0, %1 :: (store (s32) into %ir.a)
137+
138+
; That code sequence a second time, to generate a second spill slot that
139+
; will get coloured and merged.
140+
%2:i64regs = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
141+
142+
%22:i64regs = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
143+
STXri %stack.0.a, 0, %22 :: (store (s64) into %ir.a)
144+
145+
STri %stack.0.a, 0, %2 :: (store (s32) into %ir.a)
146+
147+
STri %stack.0.a, 0, $i0 :: (store (s32) into %ir.a)
148+
STri %stack.0.a, 0, $i1 :: (store (s32) into %ir.a)
149+
STri %stack.0.a, 0, $i3 :: (store (s32) into %ir.a)
150+
STri %stack.0.a, 0, $i4 :: (store (s32) into %ir.a)
151+
STri %stack.0.a, 0, $i5 :: (store (s32) into %ir.a)
152+
STri %stack.0.a, 0, $i6 :: (store (s32) into %ir.a)
153+
STri %stack.0.a, 0, $i7 :: (store (s32) into %ir.a)
154+
STri %stack.0.a, 0, $g0 :: (store (s32) into %ir.a)
155+
STri %stack.0.a, 0, $g1 :: (store (s32) into %ir.a)
156+
STri %stack.0.a, 0, $g2 :: (store (s32) into %ir.a)
157+
STri %stack.0.a, 0, $g3 :: (store (s32) into %ir.a)
158+
STri %stack.0.a, 0, $g4 :: (store (s32) into %ir.a)
159+
STri %stack.0.a, 0, $g5 :: (store (s32) into %ir.a)
160+
STri %stack.0.a, 0, $g6 :: (store (s32) into %ir.a)
161+
STri %stack.0.a, 0, $g7 :: (store (s32) into %ir.a)
162+
STri %stack.0.a, 0, $l0 :: (store (s32) into %ir.a)
163+
STri %stack.0.a, 0, $l1 :: (store (s32) into %ir.a)
164+
STri %stack.0.a, 0, $l2 :: (store (s32) into %ir.a)
165+
STri %stack.0.a, 0, $l3 :: (store (s32) into %ir.a)
166+
STri %stack.0.a, 0, $l4 :: (store (s32) into %ir.a)
167+
STri %stack.0.a, 0, $l5 :: (store (s32) into %ir.a)
168+
STri %stack.0.a, 0, $l6 :: (store (s32) into %ir.a)
169+
STri %stack.0.a, 0, $l7 :: (store (s32) into %ir.a)
170+
STri %stack.0.a, 0, $o0 :: (store (s32) into %ir.a)
171+
STri %stack.0.a, 0, $o1 :: (store (s32) into %ir.a)
172+
STri %stack.0.a, 0, $o2 :: (store (s32) into %ir.a)
173+
STri %stack.0.a, 0, $o3 :: (store (s32) into %ir.a)
174+
STri %stack.0.a, 0, $o4 :: (store (s32) into %ir.a)
175+
STri %stack.0.a, 0, $o5 :: (store (s32) into %ir.a)
176+
STri %stack.0.a, 0, $o6 :: (store (s32) into %ir.a)
177+
STri %stack.0.a, 0, $o7 :: (store (s32) into %ir.a)
178+
RETL 8, implicit $i0
179+
...

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