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Fix "Cannot select" crash on bitcast between f64 and int vector types (#201509)
All of i64, f64, v2i32, v4i16, v8i8 are assigned to the DoubleRegs register class (64-bit register pairs). A bitcast between any two of these types is a machine-level no-op (ie. the same physical register is reinterpreted with a different type). HexagonPatterns.td had NopCast_pat entries for all int-to-int bitcasts within DoubleRegs, and explicit patterns for f64 <-> i64, but was missing patterns for f64 <-> v2i32, f64 <-> v4i16, and f64 <-> v8i8. The same gap existed in IntRegs for f32 <-> v2i16 and f32 <-> v4i8. Without a tableGen pattern for "f64 = bitcast v2i32" node, the instruction selector crashed with: LLVM ERROR: Cannot select: t26: f64 = bitcast t6 t6: v2i32,ch = CopyFromReg t0, Register:v2i32 %2 Fix by adding the five missing NopCast_pat entries. Fixes: #195495
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‎llvm/lib/Target/Hexagon/HexagonPatterns.td‎

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@@ -530,17 +530,22 @@ def: Pat<(i64 (bitconvert F64:$v)), (I64:$v)>;
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def: Pat<(f64 (bitconvert I64:$v)), (F64:$v)>;
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// Bit convert 32- and 64-bit types.
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// All of these are bitcastable to one another: i32, v2i16, v4i8.
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// All of these are bitcastable to one another: i32, f32, v2i16, v4i8.
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defm: NopCast_pat<i32, v2i16, IntRegs>;
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defm: NopCast_pat<i32, v4i8, IntRegs>;
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defm: NopCast_pat<v2i16, v4i8, IntRegs>;
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// All of these are bitcastable to one another: i64, v2i32, v4i16, v8i8.
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defm: NopCast_pat<f32, v2i16, IntRegs>;
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defm: NopCast_pat<f32, v4i8, IntRegs>;
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// All of these are bitcastable to one another: i64, f64, v2i32, v4i16, v8i8.
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defm: NopCast_pat<i64, v2i32, DoubleRegs>;
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defm: NopCast_pat<i64, v4i16, DoubleRegs>;
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defm: NopCast_pat<i64, v8i8, DoubleRegs>;
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defm: NopCast_pat<v2i32, v4i16, DoubleRegs>;
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defm: NopCast_pat<v2i32, v8i8, DoubleRegs>;
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defm: NopCast_pat<v4i16, v8i8, DoubleRegs>;
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defm: NopCast_pat<f64, v2i32, DoubleRegs>;
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defm: NopCast_pat<f64, v4i16, DoubleRegs>;
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defm: NopCast_pat<f64, v8i8, DoubleRegs>;
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// --(3) Extend/truncate/saturate ----------------------------------------

‎llvm/test/CodeGen/Hexagon/bitcast-f64-vector.ll‎

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; RUN: llc -mtriple=hexagon -mcpu=hexagonv68 -O3 < %s | FileCheck %s
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; Verify that bitcasts between f64 and the integer vector types that share the
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; DoubleRegs register class (v2i32, v4i16, v8i8) are treated as no-ops by the
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; instruction selector and do not cause a "Cannot select" crash.
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;
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; All of i64, f64, v2i32, v4i16, v8i8 live in DoubleRegs (64-bit register
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; pairs). A bitcast between any two of them is a pure reinterpretation of the
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; same 64 bits. Therefore no instruction is emitted.
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;
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; Regression test for: llvm.org/PR195495
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; llc -mtriple=hexagon -mcpu=hexagonv68 -O3 crashed with
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; "Cannot select: f64 = bitcast v2i32" when compiling Eigen's packetmath.
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; CHECK-LABEL: test_v2i32_to_f64:
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; CHECK: dfcmp
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; CHECK: jumpr r31
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define i1 @test_v2i32_to_f64(<2 x i32> %a) {
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%bc = bitcast <2 x i32> %a to double
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%cmp = fcmp une double %bc, 0.0
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ret i1 %cmp
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}
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; f64->v2i32 is a no-op: the argument is already in a DoubleReg pair.
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; CHECK-LABEL: test_f64_to_v2i32:
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; CHECK-NOT: combine
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; CHECK: jumpr r31
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define <2 x i32> @test_f64_to_v2i32(double %a) {
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%bc = bitcast double %a to <2 x i32>
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ret <2 x i32> %bc
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}
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; CHECK-LABEL: test_v4i16_to_f64:
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; CHECK: dfcmp
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; CHECK: jumpr r31
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define i1 @test_v4i16_to_f64(<4 x i16> %a) {
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%bc = bitcast <4 x i16> %a to double
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%cmp = fcmp une double %bc, 0.0
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ret i1 %cmp
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}
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; CHECK-LABEL: test_v8i8_to_f64:
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; CHECK: dfcmp
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; CHECK: jumpr r31
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define i1 @test_v8i8_to_f64(<8 x i8> %a) {
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%bc = bitcast <8 x i8> %a to double
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%cmp = fcmp une double %bc, 0.0
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ret i1 %cmp
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}
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; Regression test: the original crash.
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; <4 x i32> is passed in two v2i32 DoubleReg pairs; after type-legalizing
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; <2 x f64> setcc into two scalar f64 setcc ops, each f64 operand is produced
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; by a "f64 = bitcast v2i32" node that previously had no matching pattern.
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; CHECK-LABEL: test_packetmath_reduced:
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; CHECK: dfcmp
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; CHECK: jumpr r31
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define <2 x i1> @test_packetmath_reduced(<4 x i32> %arg) {
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entry:
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%bc = bitcast <4 x i32> %arg to <2 x double>
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%cmp = fcmp une <2 x double> %bc, zeroinitializer
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ret <2 x i1> %cmp
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}

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