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[Hexagon] Add coverage tests for CodeGen passes (#183951)
Add tests targeting specific Hexagon CodeGen passes with low coverage: - peephole-sxtw-combine.mir: HexagonPeephole pass exercising SXTW removal, combine generation, and LSR copy patterns. Improves HexagonPeephole.cpp line coverage from 63.89% to 99.31%. - vec-print-wq.ll: HexagonVectorPrint pass with V (single vector) and W (double vector) register printing via 128b HVX. Improves HexagonVectorPrint.cpp line coverage from 71.19% to 87.29%. - tfr-cleanup-double-imm.mir: HexagonTfrCleanup pass exercising 64-bit immediate rewrite paths. Improves HexagonTfrCleanup.cpp line coverage from 80.85% to 88.30%. - cfgopt-newpt-invert.ll: HexagonCFGOptimizer pass exercising branch inversion with new-value predicate transfers.
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‎llvm/test/CodeGen/Hexagon/cfgopt-newpt-invert.ll‎

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; RUN: llc -mtriple=hexagon -hexagon-initial-cfg-cleanup=0 -O2 < %s \
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; RUN: | FileCheck %s
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; Test coverage for HexagonCFGOptimizer: exercise the J2_jumptnewpt/J2_jumpfnewpt
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; branch inversion path. The CFG optimizer should invert a conditional branch
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; to eliminate an unconditional jump block.
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; CHECK-LABEL: test_cfgopt_newpt:
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; CHECK: if ({{!?}}p0
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define i32 @test_cfgopt_newpt(i32 %a, i32 %b, i32 %c) #0 {
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entry:
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%cmp = icmp sgt i32 %a, %b
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br i1 %cmp, label %if.then, label %if.else
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if.then:
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%add = add nsw i32 %a, %c
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br label %return
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if.else:
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%sub = sub nsw i32 %b, %c
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%mul = mul nsw i32 %sub, 3
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br label %return
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return:
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%retval = phi i32 [ %add, %if.then ], [ %mul, %if.else ]
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ret i32 %retval
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}
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; Exercise the case2 path of CFG optimizer where JumpAroundTarget has a single
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; predecessor and a single successor with an unconditional jump.
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; CHECK-LABEL: test_cfgopt_case2:
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; CHECK: if ({{!?}}p0
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define i32 @test_cfgopt_case2(i32 %a, i32 %b, ptr %p) #0 {
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entry:
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%cmp = icmp eq i32 %a, 0
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br i1 %cmp, label %if.then, label %if.else
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if.then:
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store i32 %b, ptr %p, align 4
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br label %merge
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if.else:
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%add = add i32 %a, %b
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store i32 %add, ptr %p, align 4
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br label %merge
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merge:
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%val = load i32, ptr %p, align 4
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ret i32 %val
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}

‎llvm/test/CodeGen/Hexagon/peephole-sxtw-combine.mir‎

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# RUN: llc -mtriple=hexagon -run-pass hexagon-peephole \
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# RUN: -disable-hexagon-optszext=false \
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# RUN: -disable-hexagon-opt-ext-to-64=false -o - %s | FileCheck %s
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# Test coverage for HexagonPeephole:
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# 1) SXTW + COPY isub_lo optimization
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# 2) A4_combineir(0, r) + COPY isub_lo optimization
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# 3) S2_lsr_i_p(d, 32) + COPY isub_lo -> COPY isub_hi
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--- |
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define void @test_sxtw_copy() { ret void }
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define void @test_combine_copy() { ret void }
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define void @test_lsr_copy() { ret void }
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...
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---
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# SXTW + COPY isub_lo should be peepholed: the COPY should use the
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# original 32-bit source directly instead of extracting from the sxtw result.
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# CHECK-LABEL: name: test_sxtw_copy
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# CHECK: %2:intregs = COPY %0
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name: test_sxtw_copy
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tracksRegLiveness: true
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registers:
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- { id: 0, class: intregs }
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- { id: 1, class: doubleregs }
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- { id: 2, class: intregs }
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body: |
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bb.0:
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liveins: $r0
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%0:intregs = COPY $r0
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%1:doubleregs = A2_sxtw %0
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%2:intregs = COPY %1.isub_lo
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$r0 = COPY %2
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J2_jumpr $r31, implicit-def dead $pc, implicit killed $r0
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...
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---
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# A4_combineir(0, r) + COPY isub_lo optimization: the COPY should use
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# the 32-bit source register directly.
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# CHECK-LABEL: name: test_combine_copy
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# CHECK: %2:intregs = COPY %0
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name: test_combine_copy
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tracksRegLiveness: true
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registers:
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- { id: 0, class: intregs }
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- { id: 1, class: doubleregs }
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- { id: 2, class: intregs }
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body: |
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bb.0:
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liveins: $r0
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%0:intregs = COPY $r0
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%1:doubleregs = A4_combineir 0, %0
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%2:intregs = COPY %1.isub_lo
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$r0 = COPY %2
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J2_jumpr $r31, implicit-def dead $pc, implicit killed $r0
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...
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---
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# S2_lsr_i_p(d, 32) + COPY isub_lo should be transformed to
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# COPY isub_hi from the original double register.
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# CHECK-LABEL: name: test_lsr_copy
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# CHECK: %2:intregs = COPY %0.isub_hi
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name: test_lsr_copy
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tracksRegLiveness: true
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registers:
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- { id: 0, class: doubleregs }
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- { id: 1, class: doubleregs }
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- { id: 2, class: intregs }
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body: |
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bb.0:
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liveins: $d0
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%0:doubleregs = COPY $d0
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%1:doubleregs = S2_lsr_i_p %0, 32
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%2:intregs = COPY %1.isub_lo
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$r0 = COPY %2
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J2_jumpr $r31, implicit-def dead $pc, implicit killed $r0
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...

‎llvm/test/CodeGen/Hexagon/tfr-cleanup-double-imm.mir‎

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# RUN: llc -mtriple=hexagon -run-pass tfr-cleanup -o - %s | FileCheck %s
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# Test coverage for HexagonTfrCleanup: exercise the 64-bit register
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# immediate rewrite paths including the A2_combineii case and the
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# A2_tfrpi case.
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--- |
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define void @test_double_imm() { ret void }
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define void @test_combine_imm() { ret void }
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define void @test_self_copy() { ret void }
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...
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---
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# Test: 64-bit register copy rewritten to A2_tfrpi when source holds
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# a small immediate (fits in int8).
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# CHECK-LABEL: name: test_double_imm
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# CHECK: A2_tfrpi
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name: test_double_imm
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tracksRegLiveness: true
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body: |
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bb.0:
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$r0 = A2_tfrsi 3
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$r1 = A2_tfrsi 0
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$d1 = A2_tfrp $d0
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...
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---
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# Test: 64-bit register copy rewritten to A2_combineii when the source
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# value has both halves fitting in int8 but the full value does not.
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# CHECK-LABEL: name: test_combine_imm
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# CHECK: A2_combineii
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name: test_combine_imm
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tracksRegLiveness: true
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body: |
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bb.0:
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$r0 = A2_tfrsi 5
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$r1 = A2_tfrsi 7
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$d1 = A2_tfrp $d0
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...
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---
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# Test: eraseIfRedundant - self-assignment A2_tfr should be removed.
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# CHECK-LABEL: name: test_self_copy
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# CHECK-NOT: A2_tfr $r0, $r0
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name: test_self_copy
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $r0
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$r0 = A2_tfr $r0
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J2_jumpr $r31, implicit-def dead $pc
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...

‎llvm/test/CodeGen/Hexagon/vec-print-wq.ll‎

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; RUN: llc -mtriple=hexagon -mcpu=hexagonv68 -mattr=+hvxv68,+hvx-length128b \
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; RUN: -enable-hexagon-vector-print < %s | FileCheck %s
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; Test coverage for HexagonVectorPrint: exercise the W (double vector)
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; and V (single vector) register printing paths.
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; Use two stores so that the V result is not entirely consumed by a .new
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; store, leaving a live V register for the vector-print pass to instrument.
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; CHECK-LABEL: test_vecprint_v:
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; CHECK: InlineAsm Start
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; CHECK: .word
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; CHECK: InlineAsm End
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define void @test_vecprint_v(<32 x i32> %a, <32 x i32> %b, ptr %p, ptr %q) #0 {
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entry:
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%add = add <32 x i32> %a, %b
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store <32 x i32> %add, ptr %p, align 128
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store <32 x i32> %add, ptr %q, align 128
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ret void
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}
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; The W register case should emit inline asm blocks for each V sub-register.
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; CHECK-LABEL: test_vecprint_w:
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; CHECK: InlineAsm Start
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; CHECK: .word
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; CHECK: InlineAsm End
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; CHECK: InlineAsm Start
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; CHECK: .word
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; CHECK: InlineAsm End
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define void @test_vecprint_w(<64 x i32> %a, <64 x i32> %b, ptr %p) #0 {
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entry:
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%add = add <64 x i32> %a, %b
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store <64 x i32> %add, ptr %p, align 128
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ret void
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}
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attributes #0 = { nounwind }

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