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| 1 | +//===- llvm/CodeGen/GlobalISel/RegBankSelectFast.cpp ----------------------===// |
| 2 | +// |
| 3 | +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| 4 | +// See https://llvm.org/LICENSE.txt for license information. |
| 5 | +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| 6 | +// |
| 7 | +//===----------------------------------------------------------------------===// |
| 8 | +/// \file |
| 9 | +/// This file implements a trivial fast register bank selector. |
| 10 | +//===----------------------------------------------------------------------===// |
| 11 | + |
| 12 | +#include "llvm/CodeGen/GlobalISel/RegBankSelectFast.h" |
| 13 | +#include "llvm/ADT/PostOrderIterator.h" |
| 14 | +#include "llvm/ADT/STLExtras.h" |
| 15 | +#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" |
| 16 | +#include "llvm/CodeGen/GlobalISel/RegBankSelect.h" |
| 17 | +#include "llvm/CodeGen/MachineRegisterInfo.h" |
| 18 | +#include "llvm/CodeGen/RegisterBankInfo.h" |
| 19 | +#include "llvm/CodeGen/TargetSubtargetInfo.h" |
| 20 | +#include "llvm/InitializePasses.h" |
| 21 | +#include "llvm/Support/Debug.h" |
| 22 | + |
| 23 | +#define DEBUG_TYPE "regbankselectfast" |
| 24 | + |
| 25 | +using namespace llvm; |
| 26 | + |
| 27 | +namespace { |
| 28 | + |
| 29 | +class FallbackRegBankSelect final : public RegBankSelect { |
| 30 | +public: |
| 31 | + bool runOnCurrentFunction(MachineFunction &MF) { |
| 32 | + init(MF); |
| 33 | + return assignRegisterBanks(MF); |
| 34 | + } |
| 35 | +}; |
| 36 | + |
| 37 | +} // end anonymous namespace |
| 38 | + |
| 39 | +char RegBankSelectFast::ID = 0; |
| 40 | +INITIALIZE_PASS_BEGIN(RegBankSelectFast, DEBUG_TYPE, |
| 41 | + "Fast register bank selection", false, false) |
| 42 | +INITIALIZE_PASS_END(RegBankSelectFast, DEBUG_TYPE, |
| 43 | + "Fast register bank selection", false, false) |
| 44 | + |
| 45 | +void RegBankSelectFast::getAnalysisUsage(AnalysisUsage &AU) const { |
| 46 | + getSelectionDAGFallbackAnalysisUsage(AU); |
| 47 | + MachineFunctionPass::getAnalysisUsage(AU); |
| 48 | +} |
| 49 | + |
| 50 | +static bool assignInstr(MachineInstr &MI, MachineIRBuilder &MIRBuilder, |
| 51 | + const RegisterBankInfo &RBI, |
| 52 | + const TargetRegisterInfo &TRI, |
| 53 | + MachineRegisterInfo &MRI) { |
| 54 | + LLVM_DEBUG(dbgs() << "Assign: " << MI); |
| 55 | + |
| 56 | + const RegisterBankInfo::InstructionMapping &Mapping = RBI.getInstrMapping(MI); |
| 57 | + for (unsigned OpIdx = 0, End = Mapping.getNumOperands(); OpIdx != End; |
| 58 | + ++OpIdx) { |
| 59 | + MachineOperand &MO = MI.getOperand(OpIdx); |
| 60 | + if (!MO.isReg()) |
| 61 | + continue; |
| 62 | + Register Reg = MO.getReg(); |
| 63 | + if (!Reg || Reg.isPhysical()) |
| 64 | + continue; |
| 65 | + |
| 66 | + const RegisterBankInfo::ValueMapping &ValMapping = |
| 67 | + Mapping.getOperandMapping(OpIdx); |
| 68 | + if (!ValMapping.isValid() || ValMapping.NumBreakDowns != 1 || |
| 69 | + !ValMapping.BreakDown[0].RegBank) |
| 70 | + return false; |
| 71 | + |
| 72 | + const RegisterBank *CurrentRB = RBI.getRegBank(Reg, MRI, TRI); |
| 73 | + const RegisterBank *DesiredRB = ValMapping.BreakDown[0].RegBank; |
| 74 | + // RegBankSelectFast only assigns previously-unbanked regs. If a default |
| 75 | + // mapping wants a different bank than one already assigned, fall back to |
| 76 | + // full RegBankSelect so it can repair the conflict. |
| 77 | + if (CurrentRB && CurrentRB != DesiredRB && |
| 78 | + Mapping.getID() == RegisterBankInfo::DefaultMappingID) |
| 79 | + return false; |
| 80 | + if (!CurrentRB) |
| 81 | + MRI.setRegBank(Reg, *DesiredRB); |
| 82 | + } |
| 83 | + |
| 84 | + if (Mapping.getID() != RegisterBankInfo::DefaultMappingID) { |
| 85 | + RegisterBankInfo::OperandsMapper OpdMapper(MI, Mapping, MRI); |
| 86 | + RBI.applyMapping(MIRBuilder, OpdMapper); |
| 87 | + } |
| 88 | + |
| 89 | + return true; |
| 90 | +} |
| 91 | + |
| 92 | +bool RegBankSelectFast::runOnMachineFunction(MachineFunction &MF) { |
| 93 | + if (MF.getProperties().hasFailedISel()) |
| 94 | + return false; |
| 95 | + |
| 96 | + const RegisterBankInfo &RBI = *MF.getSubtarget().getRegBankInfo(); |
| 97 | + const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); |
| 98 | + |
| 99 | + MachineRegisterInfo &MRI = MF.getRegInfo(); |
| 100 | + MachineIRBuilder MIRBuilder(MF); |
| 101 | + |
| 102 | + ReversePostOrderTraversal<MachineFunction *> RPOT(&MF); |
| 103 | + for (MachineBasicBlock *MBB : RPOT) { |
| 104 | + MIRBuilder.setMBB(*MBB); |
| 105 | + SmallVector<MachineInstr *> WorkList( |
| 106 | + make_pointer_range(reverse(MBB->instrs()))); |
| 107 | + |
| 108 | + while (!WorkList.empty()) { |
| 109 | + MachineInstr &MI = *WorkList.pop_back_val(); |
| 110 | + |
| 111 | + // Ignore target-specific post-isel instructions: they should use proper |
| 112 | + // regclasses. |
| 113 | + if (isTargetSpecificOpcode(MI.getOpcode()) && !MI.isPreISelOpcode()) |
| 114 | + continue; |
| 115 | + |
| 116 | + // Ignore inline asm instructions: they should use physical |
| 117 | + // registers/regclasses |
| 118 | + if (MI.isInlineAsm()) |
| 119 | + continue; |
| 120 | + |
| 121 | + // Ignore IMPLICIT_DEF which must have a regclass. |
| 122 | + if (MI.isImplicitDef()) |
| 123 | + continue; |
| 124 | + |
| 125 | + if (!assignInstr(MI, MIRBuilder, RBI, TRI, MRI)) { |
| 126 | + LLVM_DEBUG(dbgs() << "Falling back to full RegBankSelect for " |
| 127 | + << MF.getName() << " after failing on: " << MI); |
| 128 | + FallbackRegBankSelect FallbackRBS; |
| 129 | + return FallbackRBS.runOnCurrentFunction(MF); |
| 130 | + } |
| 131 | + } |
| 132 | + } |
| 133 | + |
| 134 | + return true; |
| 135 | +} |
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