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rnkrnk
committedFeb 1, 2018
Merging r323155:
------------------------------------------------------------------------ r323155 | chandlerc | 2018-01-22 14:05:25 -0800 (Mon, 22 Jan 2018) | 133 lines Introduce the "retpoline" x86 mitigation technique for variant #2 of the speculative execution vulnerabilities disclosed today, specifically identified by CVE-2017-5715, "Branch Target Injection", and is one of the two halves to Spectre.. Summary: First, we need to explain the core of the vulnerability. Note that this is a very incomplete description, please see the Project Zero blog post for details: https://googleprojectzero.blogspot.com/2018/01/reading-privileged-memory-with-side.html The basis for branch target injection is to direct speculative execution of the processor to some "gadget" of executable code by poisoning the prediction of indirect branches with the address of that gadget. The gadget in turn contains an operation that provides a side channel for reading data. Most commonly, this will look like a load of secret data followed by a branch on the loaded value and then a load of some predictable cache line. The attacker then uses timing of the processors cache to determine which direction the branch took *in the speculative execution*, and in turn what one bit of the loaded value was. Due to the nature of these timing side channels and the branch predictor on Intel processors, this allows an attacker to leak data only accessible to a privileged domain (like the kernel) back into an unprivileged domain. The goal is simple: avoid generating code which contains an indirect branch that could have its prediction poisoned by an attacker. In many cases, the compiler can simply use directed conditional branches and a small search tree. LLVM already has support for lowering switches in this way and the first step of this patch is to disable jump-table lowering of switches and introduce a pass to rewrite explicit indirectbr sequences into a switch over integers. However, there is no fully general alternative to indirect calls. We introduce a new construct we call a "retpoline" to implement indirect calls in a non-speculatable way. It can be thought of loosely as a trampoline for indirect calls which uses the RET instruction on x86. Further, we arrange for a specific call->ret sequence which ensures the processor predicts the return to go to a controlled, known location. The retpoline then "smashes" the return address pushed onto the stack by the call with the desired target of the original indirect call. The result is a predicted return to the next instruction after a call (which can be used to trap speculative execution within an infinite loop) and an actual indirect branch to an arbitrary address. On 64-bit x86 ABIs, this is especially easily done in the compiler by using a guaranteed scratch register to pass the target into this device. For 32-bit ABIs there isn't a guaranteed scratch register and so several different retpoline variants are introduced to use a scratch register if one is available in the calling convention and to otherwise use direct stack push/pop sequences to pass the target address. This "retpoline" mitigation is fully described in the following blog post: https://support.google.com/faqs/answer/7625886 We also support a target feature that disables emission of the retpoline thunk by the compiler to allow for custom thunks if users want them. These are particularly useful in environments like kernels that routinely do hot-patching on boot and want to hot-patch their thunk to different code sequences. They can write this custom thunk and use `-mretpoline-external-thunk` *in addition* to `-mretpoline`. In this case, on x86-64 thu thunk names must be: ``` __llvm_external_retpoline_r11 ``` or on 32-bit: ``` __llvm_external_retpoline_eax __llvm_external_retpoline_ecx __llvm_external_retpoline_edx __llvm_external_retpoline_push ``` And the target of the retpoline is passed in the named register, or in the case of the `push` suffix on the top of the stack via a `pushl` instruction. There is one other important source of indirect branches in x86 ELF binaries: the PLT. These patches also include support for LLD to generate PLT entries that perform a retpoline-style indirection. The only other indirect branches remaining that we are aware of are from precompiled runtimes (such as crt0.o and similar). The ones we have found are not really attackable, and so we have not focused on them here, but eventually these runtimes should also be replicated for retpoline-ed configurations for completeness. For kernels or other freestanding or fully static executables, the compiler switch `-mretpoline` is sufficient to fully mitigate this particular attack. For dynamic executables, you must compile *all* libraries with `-mretpoline` and additionally link the dynamic executable and all shared libraries with LLD and pass `-z retpolineplt` (or use similar functionality from some other linker). We strongly recommend also using `-z now` as non-lazy binding allows the retpoline-mitigated PLT to be substantially smaller. When manually apply similar transformations to `-mretpoline` to the Linux kernel we observed very small performance hits to applications running typical workloads, and relatively minor hits (approximately 2%) even for extremely syscall-heavy applications. This is largely due to the small number of indirect branches that occur in performance sensitive paths of the kernel. When using these patches on statically linked applications, especially C++ applications, you should expect to see a much more dramatic performance hit. For microbenchmarks that are switch, indirect-, or virtual-call heavy we have seen overheads ranging from 10% to 50%. However, real-world workloads exhibit substantially lower performance impact. Notably, techniques such as PGO and ThinLTO dramatically reduce the impact of hot indirect calls (by speculatively promoting them to direct calls) and allow optimized search trees to be used to lower switches. If you need to deploy these techniques in C++ applications, we *strongly* recommend that you ensure all hot call targets are statically linked (avoiding PLT indirection) and use both PGO and ThinLTO. Well tuned servers using all of these techniques saw 5% - 10% overhead from the use of retpoline. We will add detailed documentation covering these components in subsequent patches, but wanted to make the core functionality available as soon as possible. Happy for more code review, but we'd really like to get these patches landed and backported ASAP for obvious reasons. We're planning to backport this to both 6.0 and 5.0 release streams and get a 5.0 release with just this cherry picked ASAP for distros and vendors. This patch is the work of a number of people over the past month: Eric, Reid, Rui, and myself. I'm mailing it out as a single commit due to the time sensitive nature of landing this and the need to backport it. Huge thanks to everyone who helped out here, and everyone at Intel who helped out in discussions about how to craft this. Also, credit goes to Paul Turner (at Google, but not an LLVM contributor) for much of the underlying retpoline design. Reviewers: echristo, rnk, ruiu, craig.topper, DavidKreitzer Subscribers: sanjoy, emaste, mcrosier, mgorny, mehdi_amini, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D41723 ------------------------------------------------------------------------ llvm-svn: 324007
1 parent c8574de commit 507d5d8

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Diff for: ‎llvm/include/llvm/CodeGen/Passes.h

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@@ -420,6 +420,9 @@ namespace llvm {
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/// shuffles.
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FunctionPass *createExpandReductionsPass();
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// This pass expands indirectbr instructions.
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FunctionPass *createIndirectBrExpandPass();
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} // End llvm namespace
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#endif

Diff for: ‎llvm/include/llvm/CodeGen/TargetPassConfig.h

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@@ -406,6 +406,13 @@ class TargetPassConfig : public ImmutablePass {
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/// immediately before machine code is emitted.
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virtual void addPreEmitPass() { }
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/// Targets may add passes immediately before machine code is emitted in this
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/// callback. This is called even later than `addPreEmitPass`.
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// FIXME: Rename `addPreEmitPass` to something more sensible given its actual
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// position and remove the `2` suffix here as this callback is what
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// `addPreEmitPass` *should* be but in reality isn't.
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virtual void addPreEmitPass2() {}
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/// Utilities for targets to add passes to the pass manager.
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///
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Diff for: ‎llvm/include/llvm/InitializePasses.h

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@@ -157,6 +157,7 @@ void initializeIVUsersWrapperPassPass(PassRegistry&);
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void initializeIfConverterPass(PassRegistry&);
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void initializeImplicitNullChecksPass(PassRegistry&);
159159
void initializeIndVarSimplifyLegacyPassPass(PassRegistry&);
160+
void initializeIndirectBrExpandPassPass(PassRegistry&);
160161
void initializeInductiveRangeCheckEliminationPass(PassRegistry&);
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void initializeInferAddressSpacesPass(PassRegistry&);
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void initializeInferFunctionAttrsLegacyPassPass(PassRegistry&);

Diff for: ‎llvm/include/llvm/Target/TargetLowering.h

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@@ -799,7 +799,7 @@ class TargetLoweringBase {
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}
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801801
/// Return true if lowering to a jump table is allowed.
802-
bool areJTsAllowed(const Function *Fn) const {
802+
virtual bool areJTsAllowed(const Function *Fn) const {
803803
if (Fn->getFnAttribute("no-jump-tables").getValueAsString() == "true")
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return false;
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Diff for: ‎llvm/include/llvm/Target/TargetSubtargetInfo.h

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@@ -172,6 +172,9 @@ class TargetSubtargetInfo : public MCSubtargetInfo {
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/// \brief True if the subtarget should run the atomic expansion pass.
173173
virtual bool enableAtomicExpand() const;
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175+
/// True if the subtarget should run the indirectbr expansion pass.
176+
virtual bool enableIndirectBrExpand() const;
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/// \brief Override generic scheduling policy within a region.
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///
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/// This is a convenient way for targets that don't provide any custom

Diff for: ‎llvm/lib/CodeGen/CMakeLists.txt

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@@ -34,6 +34,7 @@ add_llvm_library(LLVMCodeGen
3434
GlobalMerge.cpp
3535
IfConversion.cpp
3636
ImplicitNullChecks.cpp
37+
IndirectBrExpandPass.cpp
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InlineSpiller.cpp
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InterferenceCache.cpp
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InterleavedAccessPass.cpp

Diff for: ‎llvm/lib/CodeGen/CodeGen.cpp

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@@ -39,6 +39,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
3939
initializeGCModuleInfoPass(Registry);
4040
initializeIfConverterPass(Registry);
4141
initializeImplicitNullChecksPass(Registry);
42+
initializeIndirectBrExpandPassPass(Registry);
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initializeInterleavedAccessPass(Registry);
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initializeLiveDebugValuesPass(Registry);
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initializeLiveDebugVariablesPass(Registry);

Diff for: ‎llvm/lib/CodeGen/IndirectBrExpandPass.cpp

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@@ -0,0 +1,221 @@
1+
//===- IndirectBrExpandPass.cpp - Expand indirectbr to switch -------------===//
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//
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// The LLVM Compiler Infrastructure
4+
//
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// This file is distributed under the University of Illinois Open Source
6+
// License. See LICENSE.TXT for details.
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//
8+
//===----------------------------------------------------------------------===//
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/// \file
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///
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/// Implements an expansion pass to turn `indirectbr` instructions in the IR
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/// into `switch` instructions. This works by enumerating the basic blocks in
13+
/// a dense range of integers, replacing each `blockaddr` constant with the
14+
/// corresponding integer constant, and then building a switch that maps from
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/// the integers to the actual blocks. All of the indirectbr instructions in the
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/// function are redirected to this common switch.
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///
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/// While this is generically useful if a target is unable to codegen
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/// `indirectbr` natively, it is primarily useful when there is some desire to
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/// get the builtin non-jump-table lowering of a switch even when the input
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/// source contained an explicit indirect branch construct.
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///
23+
/// Note that it doesn't make any sense to enable this pass unless a target also
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/// disables jump-table lowering of switches. Doing that is likely to pessimize
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/// the code.
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///
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//===----------------------------------------------------------------------===//
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29+
#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/Sequence.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include "llvm/IR/BasicBlock.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/IRBuilder.h"
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#include "llvm/IR/InstIterator.h"
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#include "llvm/IR/Instruction.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
47+
48+
#define DEBUG_TYPE "indirectbr-expand"
49+
50+
namespace {
51+
52+
class IndirectBrExpandPass : public FunctionPass {
53+
const TargetLowering *TLI = nullptr;
54+
55+
public:
56+
static char ID; // Pass identification, replacement for typeid
57+
58+
IndirectBrExpandPass() : FunctionPass(ID) {
59+
initializeIndirectBrExpandPassPass(*PassRegistry::getPassRegistry());
60+
}
61+
62+
bool runOnFunction(Function &F) override;
63+
};
64+
65+
} // end anonymous namespace
66+
67+
char IndirectBrExpandPass::ID = 0;
68+
69+
INITIALIZE_PASS(IndirectBrExpandPass, DEBUG_TYPE,
70+
"Expand indirectbr instructions", false, false)
71+
72+
FunctionPass *llvm::createIndirectBrExpandPass() {
73+
return new IndirectBrExpandPass();
74+
}
75+
76+
bool IndirectBrExpandPass::runOnFunction(Function &F) {
77+
auto &DL = F.getParent()->getDataLayout();
78+
auto *TPC = getAnalysisIfAvailable<TargetPassConfig>();
79+
if (!TPC)
80+
return false;
81+
82+
auto &TM = TPC->getTM<TargetMachine>();
83+
auto &STI = *TM.getSubtargetImpl(F);
84+
if (!STI.enableIndirectBrExpand())
85+
return false;
86+
TLI = STI.getTargetLowering();
87+
88+
SmallVector<IndirectBrInst *, 1> IndirectBrs;
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90+
// Set of all potential successors for indirectbr instructions.
91+
SmallPtrSet<BasicBlock *, 4> IndirectBrSuccs;
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93+
// Build a list of indirectbrs that we want to rewrite.
94+
for (BasicBlock &BB : F)
95+
if (auto *IBr = dyn_cast<IndirectBrInst>(BB.getTerminator())) {
96+
// Handle the degenerate case of no successors by replacing the indirectbr
97+
// with unreachable as there is no successor available.
98+
if (IBr->getNumSuccessors() == 0) {
99+
(void)new UnreachableInst(F.getContext(), IBr);
100+
IBr->eraseFromParent();
101+
continue;
102+
}
103+
104+
IndirectBrs.push_back(IBr);
105+
for (BasicBlock *SuccBB : IBr->successors())
106+
IndirectBrSuccs.insert(SuccBB);
107+
}
108+
109+
if (IndirectBrs.empty())
110+
return false;
111+
112+
// If we need to replace any indirectbrs we need to establish integer
113+
// constants that will correspond to each of the basic blocks in the function
114+
// whose address escapes. We do that here and rewrite all the blockaddress
115+
// constants to just be those integer constants cast to a pointer type.
116+
SmallVector<BasicBlock *, 4> BBs;
117+
118+
for (BasicBlock &BB : F) {
119+
// Skip blocks that aren't successors to an indirectbr we're going to
120+
// rewrite.
121+
if (!IndirectBrSuccs.count(&BB))
122+
continue;
123+
124+
auto IsBlockAddressUse = [&](const Use &U) {
125+
return isa<BlockAddress>(U.getUser());
126+
};
127+
auto BlockAddressUseIt = llvm::find_if(BB.uses(), IsBlockAddressUse);
128+
if (BlockAddressUseIt == BB.use_end())
129+
continue;
130+
131+
assert(std::find_if(std::next(BlockAddressUseIt), BB.use_end(),
132+
IsBlockAddressUse) == BB.use_end() &&
133+
"There should only ever be a single blockaddress use because it is "
134+
"a constant and should be uniqued.");
135+
136+
auto *BA = cast<BlockAddress>(BlockAddressUseIt->getUser());
137+
138+
// Skip if the constant was formed but ended up not being used (due to DCE
139+
// or whatever).
140+
if (!BA->isConstantUsed())
141+
continue;
142+
143+
// Compute the index we want to use for this basic block. We can't use zero
144+
// because null can be compared with block addresses.
145+
int BBIndex = BBs.size() + 1;
146+
BBs.push_back(&BB);
147+
148+
auto *ITy = cast<IntegerType>(DL.getIntPtrType(BA->getType()));
149+
ConstantInt *BBIndexC = ConstantInt::get(ITy, BBIndex);
150+
151+
// Now rewrite the blockaddress to an integer constant based on the index.
152+
// FIXME: We could potentially preserve the uses as arguments to inline asm.
153+
// This would allow some uses such as diagnostic information in crashes to
154+
// have higher quality even when this transform is enabled, but would break
155+
// users that round-trip blockaddresses through inline assembly and then
156+
// back into an indirectbr.
157+
BA->replaceAllUsesWith(ConstantExpr::getIntToPtr(BBIndexC, BA->getType()));
158+
}
159+
160+
if (BBs.empty()) {
161+
// There are no blocks whose address is taken, so any indirectbr instruction
162+
// cannot get a valid input and we can replace all of them with unreachable.
163+
for (auto *IBr : IndirectBrs) {
164+
(void)new UnreachableInst(F.getContext(), IBr);
165+
IBr->eraseFromParent();
166+
}
167+
return true;
168+
}
169+
170+
BasicBlock *SwitchBB;
171+
Value *SwitchValue;
172+
173+
// Compute a common integer type across all the indirectbr instructions.
174+
IntegerType *CommonITy = nullptr;
175+
for (auto *IBr : IndirectBrs) {
176+
auto *ITy =
177+
cast<IntegerType>(DL.getIntPtrType(IBr->getAddress()->getType()));
178+
if (!CommonITy || ITy->getBitWidth() > CommonITy->getBitWidth())
179+
CommonITy = ITy;
180+
}
181+
182+
auto GetSwitchValue = [DL, CommonITy](IndirectBrInst *IBr) {
183+
return CastInst::CreatePointerCast(
184+
IBr->getAddress(), CommonITy,
185+
Twine(IBr->getAddress()->getName()) + ".switch_cast", IBr);
186+
};
187+
188+
if (IndirectBrs.size() == 1) {
189+
// If we only have one indirectbr, we can just directly replace it within
190+
// its block.
191+
SwitchBB = IndirectBrs[0]->getParent();
192+
SwitchValue = GetSwitchValue(IndirectBrs[0]);
193+
IndirectBrs[0]->eraseFromParent();
194+
} else {
195+
// Otherwise we need to create a new block to hold the switch across BBs,
196+
// jump to that block instead of each indirectbr, and phi together the
197+
// values for the switch.
198+
SwitchBB = BasicBlock::Create(F.getContext(), "switch_bb", &F);
199+
auto *SwitchPN = PHINode::Create(CommonITy, IndirectBrs.size(),
200+
"switch_value_phi", SwitchBB);
201+
SwitchValue = SwitchPN;
202+
203+
// Now replace the indirectbr instructions with direct branches to the
204+
// switch block and fill out the PHI operands.
205+
for (auto *IBr : IndirectBrs) {
206+
SwitchPN->addIncoming(GetSwitchValue(IBr), IBr->getParent());
207+
BranchInst::Create(SwitchBB, IBr);
208+
IBr->eraseFromParent();
209+
}
210+
}
211+
212+
// Now build the switch in the block. The block will have no terminator
213+
// already.
214+
auto *SI = SwitchInst::Create(SwitchValue, BBs[0], BBs.size(), SwitchBB);
215+
216+
// Add a case for each block.
217+
for (int i : llvm::seq<int>(1, BBs.size()))
218+
SI->addCase(ConstantInt::get(CommonITy, i + 1), BBs[i]);
219+
220+
return true;
221+
}

Diff for: ‎llvm/lib/CodeGen/TargetPassConfig.cpp

+3
Original file line numberDiff line numberDiff line change
@@ -790,6 +790,9 @@ void TargetPassConfig::addMachinePasses() {
790790
if (EnableMachineOutliner)
791791
PM->add(createMachineOutlinerPass());
792792

793+
// Add passes that directly emit MI after all other MI passes.
794+
addPreEmitPass2();
795+
793796
AddingMachinePasses = false;
794797
}
795798

Diff for: ‎llvm/lib/CodeGen/TargetSubtargetInfo.cpp

+4
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,10 @@ bool TargetSubtargetInfo::enableAtomicExpand() const {
3737
return true;
3838
}
3939

40+
bool TargetSubtargetInfo::enableIndirectBrExpand() const {
41+
return false;
42+
}
43+
4044
bool TargetSubtargetInfo::enableMachineScheduler() const {
4145
return false;
4246
}

Diff for: ‎llvm/lib/Target/X86/CMakeLists.txt

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Original file line numberDiff line numberDiff line change
@@ -57,6 +57,7 @@ set(sources
5757
X86OptimizeLEAs.cpp
5858
X86PadShortFunction.cpp
5959
X86RegisterInfo.cpp
60+
X86RetpolineThunks.cpp
6061
X86SelectionDAGInfo.cpp
6162
X86ShuffleDecodeConstantPool.cpp
6263
X86Subtarget.cpp

Diff for: ‎llvm/lib/Target/X86/X86.h

+4
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,7 @@ namespace llvm {
2222
class FunctionPass;
2323
class ImmutablePass;
2424
class InstructionSelector;
25+
class ModulePass;
2526
class PassRegistry;
2627
class X86RegisterBankInfo;
2728
class X86Subtarget;
@@ -98,6 +99,9 @@ void initializeFixupBWInstPassPass(PassRegistry &);
9899
/// encoding when possible in order to reduce code size.
99100
FunctionPass *createX86EvexToVexInsts();
100101

102+
/// This pass creates the thunks for the retpoline feature.
103+
ModulePass *createX86RetpolineThunksPass();
104+
101105
InstructionSelector *createX86InstructionSelector(const X86TargetMachine &TM,
102106
X86Subtarget &,
103107
X86RegisterBankInfo &);

Diff for: ‎llvm/lib/Target/X86/X86.td

+21
Original file line numberDiff line numberDiff line change
@@ -290,6 +290,27 @@ def FeatureERMSB
290290
"ermsb", "HasERMSB", "true",
291291
"REP MOVS/STOS are fast">;
292292

293+
// Enable mitigation of some aspects of speculative execution related
294+
// vulnerabilities by removing speculatable indirect branches. This disables
295+
// jump-table formation, rewrites explicit `indirectbr` instructions into
296+
// `switch` instructions, and uses a special construct called a "retpoline" to
297+
// prevent speculation of the remaining indirect branches (indirect calls and
298+
// tail calls).
299+
def FeatureRetpoline
300+
: SubtargetFeature<"retpoline", "UseRetpoline", "true",
301+
"Remove speculation of indirect branches from the "
302+
"generated code, either by avoiding them entirely or "
303+
"lowering them with a speculation blocking construct.">;
304+
305+
// Rely on external thunks for the emitted retpoline calls. This allows users
306+
// to provide their own custom thunk definitions in highly specialized
307+
// environments such as a kernel that does boot-time hot patching.
308+
def FeatureRetpolineExternalThunk
309+
: SubtargetFeature<
310+
"retpoline-external-thunk", "UseRetpolineExternalThunk", "true",
311+
"Enable retpoline, but with an externally provided thunk.",
312+
[FeatureRetpoline]>;
313+
293314
//===----------------------------------------------------------------------===//
294315
// X86 processors supported.
295316
//===----------------------------------------------------------------------===//

Diff for: ‎llvm/lib/Target/X86/X86AsmPrinter.h

+1
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,7 @@ class LLVM_LIBRARY_VISIBILITY X86AsmPrinter : public AsmPrinter {
3030
StackMaps SM;
3131
FaultMaps FM;
3232
std::unique_ptr<MCCodeEmitter> CodeEmitter;
33+
bool NeedsRetpoline = false;
3334

3435
// This utility class tracks the length of a stackmap instruction's 'shadow'.
3536
// It is used by the X86AsmPrinter to ensure that the stackmap shadow

Diff for: ‎llvm/lib/Target/X86/X86FastISel.cpp

+4
Original file line numberDiff line numberDiff line change
@@ -3161,6 +3161,10 @@ bool X86FastISel::fastLowerCall(CallLoweringInfo &CLI) {
31613161
(CalledFn && CalledFn->hasFnAttribute("no_caller_saved_registers")))
31623162
return false;
31633163

3164+
// Functions using retpoline should use SDISel for calls.
3165+
if (Subtarget->useRetpoline())
3166+
return false;
3167+
31643168
// Handle only C, fastcc, and webkit_js calling conventions for now.
31653169
switch (CC) {
31663170
default: return false;

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