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[RISCV][llvm] Correct code generation of fma on zvfbfa (#176716)
Currently it's mapped to normal float16 instructions. (cherry picked from commit 3bab752)
1 parent 16fcbfb commit 40f7eee

10 files changed

+143
-141
lines changed

‎llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td‎

Lines changed: 11 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1233,34 +1233,35 @@ foreach fvti = AllFloatAndBF16Vectors in {
12331233
// NOTE: We choose VFMADD because it has the most commuting freedom. So it
12341234
// works best with how TwoAddressInstructionPass tries commuting.
12351235
defvar suffix = fvti.LMul.MX # "_E" # fvti.SEW;
1236+
defvar alt = !if(!eq(fvti.Scalar, bf16), "_ALT", "");
12361237
let Predicates = GetVTypePredicates<fvti>.Predicates in {
12371238
def : Pat<(fvti.Vector (any_fma fvti.RegClass:$rs1, fvti.RegClass:$rd,
12381239
fvti.RegClass:$rs2)),
1239-
(!cast<Instruction>("PseudoVFMADD_VV_"# suffix)
1240+
(!cast<Instruction>("PseudoVFMADD" # alt # "_VV_"# suffix)
12401241
fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2,
12411242
// Value to indicate no rounding mode change in
12421243
// RISCVInsertReadWriteCSR
12431244
FRM_DYN,
12441245
fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>;
12451246
def : Pat<(fvti.Vector (any_fma fvti.RegClass:$rs1, fvti.RegClass:$rd,
12461247
(fneg fvti.RegClass:$rs2))),
1247-
(!cast<Instruction>("PseudoVFMSUB_VV_"# suffix)
1248+
(!cast<Instruction>("PseudoVFMSUB" # alt # "_VV_"# suffix)
12481249
fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2,
12491250
// Value to indicate no rounding mode change in
12501251
// RISCVInsertReadWriteCSR
12511252
FRM_DYN,
12521253
fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>;
12531254
def : Pat<(fvti.Vector (any_fma (fneg fvti.RegClass:$rs1), fvti.RegClass:$rd,
12541255
(fneg fvti.RegClass:$rs2))),
1255-
(!cast<Instruction>("PseudoVFNMADD_VV_"# suffix)
1256+
(!cast<Instruction>("PseudoVFNMADD" # alt # "_VV_"# suffix)
12561257
fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2,
12571258
// Value to indicate no rounding mode change in
12581259
// RISCVInsertReadWriteCSR
12591260
FRM_DYN,
12601261
fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>;
12611262
def : Pat<(fvti.Vector (any_fma (fneg fvti.RegClass:$rs1), fvti.RegClass:$rd,
12621263
fvti.RegClass:$rs2)),
1263-
(!cast<Instruction>("PseudoVFNMSUB_VV_"# suffix)
1264+
(!cast<Instruction>("PseudoVFNMSUB" # alt # "_VV_"# suffix)
12641265
fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2,
12651266
// Value to indicate no rounding mode change in
12661267
// RISCVInsertReadWriteCSR
@@ -1271,15 +1272,15 @@ foreach fvti = AllFloatAndBF16Vectors in {
12711272
// commutable.
12721273
def : Pat<(fvti.Vector (any_fma (SplatFPOp fvti.ScalarRegClass:$rs1),
12731274
fvti.RegClass:$rd, fvti.RegClass:$rs2)),
1274-
(!cast<Instruction>("PseudoVFMADD_V" # fvti.ScalarSuffix # "_" # suffix)
1275+
(!cast<Instruction>("PseudoVFMADD" # alt # "_V" # fvti.ScalarSuffix # "_" # suffix)
12751276
fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2,
12761277
// Value to indicate no rounding mode change in
12771278
// RISCVInsertReadWriteCSR
12781279
FRM_DYN,
12791280
fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>;
12801281
def : Pat<(fvti.Vector (any_fma (SplatFPOp fvti.ScalarRegClass:$rs1),
12811282
fvti.RegClass:$rd, (fneg fvti.RegClass:$rs2))),
1282-
(!cast<Instruction>("PseudoVFMSUB_V" # fvti.ScalarSuffix # "_" # suffix)
1283+
(!cast<Instruction>("PseudoVFMSUB" # alt # "_V" # fvti.ScalarSuffix # "_" # suffix)
12831284
fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2,
12841285
// Value to indicate no rounding mode change in
12851286
// RISCVInsertReadWriteCSR
@@ -1288,15 +1289,15 @@ foreach fvti = AllFloatAndBF16Vectors in {
12881289

12891290
def : Pat<(fvti.Vector (any_fma (SplatFPOp fvti.ScalarRegClass:$rs1),
12901291
(fneg fvti.RegClass:$rd), (fneg fvti.RegClass:$rs2))),
1291-
(!cast<Instruction>("PseudoVFNMADD_V" # fvti.ScalarSuffix # "_" # suffix)
1292+
(!cast<Instruction>("PseudoVFNMADD" # alt # "_V" # fvti.ScalarSuffix # "_" # suffix)
12921293
fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2,
12931294
// Value to indicate no rounding mode change in
12941295
// RISCVInsertReadWriteCSR
12951296
FRM_DYN,
12961297
fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>;
12971298
def : Pat<(fvti.Vector (any_fma (SplatFPOp fvti.ScalarRegClass:$rs1),
12981299
(fneg fvti.RegClass:$rd), fvti.RegClass:$rs2)),
1299-
(!cast<Instruction>("PseudoVFNMSUB_V" # fvti.ScalarSuffix # "_" # suffix)
1300+
(!cast<Instruction>("PseudoVFNMSUB" # alt # "_V" # fvti.ScalarSuffix # "_" # suffix)
13001301
fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2,
13011302
// Value to indicate no rounding mode change in
13021303
// RISCVInsertReadWriteCSR
@@ -1306,15 +1307,15 @@ foreach fvti = AllFloatAndBF16Vectors in {
13061307
// The splat might be negated.
13071308
def : Pat<(fvti.Vector (any_fma (fneg (SplatFPOp fvti.ScalarRegClass:$rs1)),
13081309
fvti.RegClass:$rd, (fneg fvti.RegClass:$rs2))),
1309-
(!cast<Instruction>("PseudoVFNMADD_V" # fvti.ScalarSuffix # "_" # suffix)
1310+
(!cast<Instruction>("PseudoVFNMADD" # alt # "_V" # fvti.ScalarSuffix # "_" # suffix)
13101311
fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2,
13111312
// Value to indicate no rounding mode change in
13121313
// RISCVInsertReadWriteCSR
13131314
FRM_DYN,
13141315
fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>;
13151316
def : Pat<(fvti.Vector (any_fma (fneg (SplatFPOp fvti.ScalarRegClass:$rs1)),
13161317
fvti.RegClass:$rd, fvti.RegClass:$rs2)),
1317-
(!cast<Instruction>("PseudoVFNMSUB_V" # fvti.ScalarSuffix # "_" # suffix)
1318+
(!cast<Instruction>("PseudoVFNMSUB" # alt # "_V" # fvti.ScalarSuffix # "_" # suffix)
13181319
fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2,
13191320
// Value to indicate no rounding mode change in
13201321
// RISCVInsertReadWriteCSR

‎llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1814,11 +1814,12 @@ multiclass VPatFPMulAddVL_VV_VF<SDPatternOperator vop, string instruction_name>
18141814
multiclass VPatFPMulAddVL_VV_VF_RM<SDPatternOperator vop, string instruction_name> {
18151815
foreach vti = AllFloatAndBF16Vectors in {
18161816
defvar suffix = vti.LMul.MX # "_E" # vti.SEW;
1817+
defvar alt = !if(!eq(vti.Scalar, bf16), "_ALT", "");
18171818
let Predicates = GetVTypePredicates<vti>.Predicates in {
18181819
def : Pat<(vti.Vector (vop vti.RegClass:$rs1, vti.RegClass:$rd,
18191820
vti.RegClass:$rs2, (vti.Mask VMV0:$vm),
18201821
VLOpFrag)),
1821-
(!cast<Instruction>(instruction_name#"_VV_"# suffix #"_MASK")
1822+
(!cast<Instruction>(instruction_name # alt # "_VV_"# suffix #"_MASK")
18221823
vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
18231824
(vti.Mask VMV0:$vm),
18241825
// Value to indicate no rounding mode change in
@@ -1830,7 +1831,7 @@ multiclass VPatFPMulAddVL_VV_VF_RM<SDPatternOperator vop, string instruction_nam
18301831
vti.RegClass:$rd, vti.RegClass:$rs2,
18311832
(vti.Mask VMV0:$vm),
18321833
VLOpFrag)),
1833-
(!cast<Instruction>(instruction_name#"_V" # vti.ScalarSuffix # "_" # suffix # "_MASK")
1834+
(!cast<Instruction>(instruction_name # alt # "_V" # vti.ScalarSuffix # "_" # suffix # "_MASK")
18341835
vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
18351836
(vti.Mask VMV0:$vm),
18361837
// Value to indicate no rounding mode change in

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmadd-sdnode.ll‎

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
77
define <1 x bfloat> @vfmadd_vv_v1bf16(<1 x bfloat> %va, <1 x bfloat> %vb, <1 x bfloat> %vc) {
88
; CHECK-LABEL: vfmadd_vv_v1bf16:
99
; CHECK: # %bb.0:
10-
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
10+
; CHECK-NEXT: vsetivli zero, 1, e16alt, mf4, ta, ma
1111
; CHECK-NEXT: vfmadd.vv v8, v9, v10
1212
; CHECK-NEXT: ret
1313
%vd = call <1 x bfloat> @llvm.fma.v1bf16(<1 x bfloat> %va, <1 x bfloat> %vb, <1 x bfloat> %vc)
@@ -17,7 +17,7 @@ define <1 x bfloat> @vfmadd_vv_v1bf16(<1 x bfloat> %va, <1 x bfloat> %vb, <1 x b
1717
define <1 x bfloat> @vfmadd_vf_v1bf16(<1 x bfloat> %va, <1 x bfloat> %vb, bfloat %c) {
1818
; CHECK-LABEL: vfmadd_vf_v1bf16:
1919
; CHECK: # %bb.0:
20-
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
20+
; CHECK-NEXT: vsetivli zero, 1, e16alt, mf4, ta, ma
2121
; CHECK-NEXT: vfmadd.vf v8, fa0, v9
2222
; CHECK-NEXT: ret
2323
%head = insertelement <1 x bfloat> poison, bfloat %c, i32 0
@@ -29,7 +29,7 @@ define <1 x bfloat> @vfmadd_vf_v1bf16(<1 x bfloat> %va, <1 x bfloat> %vb, bfloat
2929
define <2 x bfloat> @vfmadd_vv_v2bf16(<2 x bfloat> %va, <2 x bfloat> %vb, <2 x bfloat> %vc) {
3030
; CHECK-LABEL: vfmadd_vv_v2bf16:
3131
; CHECK: # %bb.0:
32-
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
32+
; CHECK-NEXT: vsetivli zero, 2, e16alt, mf4, ta, ma
3333
; CHECK-NEXT: vfmadd.vv v8, v9, v10
3434
; CHECK-NEXT: ret
3535
%vd = call <2 x bfloat> @llvm.fma.v2bf16(<2 x bfloat> %va, <2 x bfloat> %vb, <2 x bfloat> %vc)
@@ -39,7 +39,7 @@ define <2 x bfloat> @vfmadd_vv_v2bf16(<2 x bfloat> %va, <2 x bfloat> %vb, <2 x b
3939
define <2 x bfloat> @vfmadd_vf_v2bf16(<2 x bfloat> %va, <2 x bfloat> %vb, bfloat %c) {
4040
; CHECK-LABEL: vfmadd_vf_v2bf16:
4141
; CHECK: # %bb.0:
42-
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
42+
; CHECK-NEXT: vsetivli zero, 2, e16alt, mf4, ta, ma
4343
; CHECK-NEXT: vfmadd.vf v8, fa0, v9
4444
; CHECK-NEXT: ret
4545
%head = insertelement <2 x bfloat> poison, bfloat %c, i32 0
@@ -51,7 +51,7 @@ define <2 x bfloat> @vfmadd_vf_v2bf16(<2 x bfloat> %va, <2 x bfloat> %vb, bfloat
5151
define <4 x bfloat> @vfmadd_vv_v4bf16(<4 x bfloat> %va, <4 x bfloat> %vb, <4 x bfloat> %vc) {
5252
; CHECK-LABEL: vfmadd_vv_v4bf16:
5353
; CHECK: # %bb.0:
54-
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
54+
; CHECK-NEXT: vsetivli zero, 4, e16alt, mf2, ta, ma
5555
; CHECK-NEXT: vfmadd.vv v8, v9, v10
5656
; CHECK-NEXT: ret
5757
%vd = call <4 x bfloat> @llvm.fma.v4bf16(<4 x bfloat> %va, <4 x bfloat> %vb, <4 x bfloat> %vc)
@@ -61,7 +61,7 @@ define <4 x bfloat> @vfmadd_vv_v4bf16(<4 x bfloat> %va, <4 x bfloat> %vb, <4 x b
6161
define <4 x bfloat> @vfmadd_vf_v4bf16(<4 x bfloat> %va, <4 x bfloat> %vb, bfloat %c) {
6262
; CHECK-LABEL: vfmadd_vf_v4bf16:
6363
; CHECK: # %bb.0:
64-
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
64+
; CHECK-NEXT: vsetivli zero, 4, e16alt, mf2, ta, ma
6565
; CHECK-NEXT: vfmadd.vf v8, fa0, v9
6666
; CHECK-NEXT: ret
6767
%head = insertelement <4 x bfloat> poison, bfloat %c, i32 0
@@ -73,7 +73,7 @@ define <4 x bfloat> @vfmadd_vf_v4bf16(<4 x bfloat> %va, <4 x bfloat> %vb, bfloat
7373
define <8 x bfloat> @vfmadd_vv_v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, <8 x bfloat> %vc) {
7474
; CHECK-LABEL: vfmadd_vv_v8bf16:
7575
; CHECK: # %bb.0:
76-
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
76+
; CHECK-NEXT: vsetivli zero, 8, e16alt, m1, ta, ma
7777
; CHECK-NEXT: vfmadd.vv v8, v9, v10
7878
; CHECK-NEXT: ret
7979
%vd = call <8 x bfloat> @llvm.fma.v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, <8 x bfloat> %vc)
@@ -83,7 +83,7 @@ define <8 x bfloat> @vfmadd_vv_v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, <8 x b
8383
define <8 x bfloat> @vfmadd_vf_v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, bfloat %c) {
8484
; CHECK-LABEL: vfmadd_vf_v8bf16:
8585
; CHECK: # %bb.0:
86-
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
86+
; CHECK-NEXT: vsetivli zero, 8, e16alt, m1, ta, ma
8787
; CHECK-NEXT: vfmadd.vf v8, fa0, v9
8888
; CHECK-NEXT: ret
8989
%head = insertelement <8 x bfloat> poison, bfloat %c, i32 0
@@ -95,7 +95,7 @@ define <8 x bfloat> @vfmadd_vf_v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, bfloat
9595
define <16 x bfloat> @vfmadd_vv_v16bf16(<16 x bfloat> %va, <16 x bfloat> %vb, <16 x bfloat> %vc) {
9696
; CHECK-LABEL: vfmadd_vv_v16bf16:
9797
; CHECK: # %bb.0:
98-
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
98+
; CHECK-NEXT: vsetivli zero, 16, e16alt, m2, ta, ma
9999
; CHECK-NEXT: vfmadd.vv v8, v10, v12
100100
; CHECK-NEXT: ret
101101
%vd = call <16 x bfloat> @llvm.fma.v16bf16(<16 x bfloat> %va, <16 x bfloat> %vb, <16 x bfloat> %vc)
@@ -105,7 +105,7 @@ define <16 x bfloat> @vfmadd_vv_v16bf16(<16 x bfloat> %va, <16 x bfloat> %vb, <1
105105
define <16 x bfloat> @vfmadd_vf_v16bf16(<16 x bfloat> %va, <16 x bfloat> %vb, bfloat %c) {
106106
; CHECK-LABEL: vfmadd_vf_v16bf16:
107107
; CHECK: # %bb.0:
108-
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
108+
; CHECK-NEXT: vsetivli zero, 16, e16alt, m2, ta, ma
109109
; CHECK-NEXT: vfmadd.vf v8, fa0, v10
110110
; CHECK-NEXT: ret
111111
%head = insertelement <16 x bfloat> poison, bfloat %c, i32 0
@@ -117,7 +117,7 @@ define <16 x bfloat> @vfmadd_vf_v16bf16(<16 x bfloat> %va, <16 x bfloat> %vb, bf
117117
define <1 x bfloat> @vfmacc_vv_v1bf16(<1 x bfloat> %va, <1 x bfloat> %vb, <1 x bfloat> %vc) {
118118
; CHECK-LABEL: vfmacc_vv_v1bf16:
119119
; CHECK: # %bb.0:
120-
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
120+
; CHECK-NEXT: vsetivli zero, 1, e16alt, mf4, ta, ma
121121
; CHECK-NEXT: vfmacc.vv v8, v10, v9
122122
; CHECK-NEXT: ret
123123
%vd = call <1 x bfloat> @llvm.fma.v1bf16(<1 x bfloat> %vb, <1 x bfloat> %vc, <1 x bfloat> %va)
@@ -127,7 +127,7 @@ define <1 x bfloat> @vfmacc_vv_v1bf16(<1 x bfloat> %va, <1 x bfloat> %vb, <1 x b
127127
define <1 x bfloat> @vfmacc_vf_v1bf16(<1 x bfloat> %va, <1 x bfloat> %vb, bfloat %c) {
128128
; CHECK-LABEL: vfmacc_vf_v1bf16:
129129
; CHECK: # %bb.0:
130-
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
130+
; CHECK-NEXT: vsetivli zero, 1, e16alt, mf4, ta, ma
131131
; CHECK-NEXT: vfmacc.vf v8, fa0, v9
132132
; CHECK-NEXT: ret
133133
%head = insertelement <1 x bfloat> poison, bfloat %c, i32 0
@@ -139,7 +139,7 @@ define <1 x bfloat> @vfmacc_vf_v1bf16(<1 x bfloat> %va, <1 x bfloat> %vb, bfloat
139139
define <2 x bfloat> @vfmacc_vv_v2bf16(<2 x bfloat> %va, <2 x bfloat> %vb, <2 x bfloat> %vc) {
140140
; CHECK-LABEL: vfmacc_vv_v2bf16:
141141
; CHECK: # %bb.0:
142-
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
142+
; CHECK-NEXT: vsetivli zero, 2, e16alt, mf4, ta, ma
143143
; CHECK-NEXT: vfmacc.vv v8, v10, v9
144144
; CHECK-NEXT: ret
145145
%vd = call <2 x bfloat> @llvm.fma.v2bf16(<2 x bfloat> %vb, <2 x bfloat> %vc, <2 x bfloat> %va)
@@ -149,7 +149,7 @@ define <2 x bfloat> @vfmacc_vv_v2bf16(<2 x bfloat> %va, <2 x bfloat> %vb, <2 x b
149149
define <2 x bfloat> @vfmacc_vf_v2bf16(<2 x bfloat> %va, <2 x bfloat> %vb, bfloat %c) {
150150
; CHECK-LABEL: vfmacc_vf_v2bf16:
151151
; CHECK: # %bb.0:
152-
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
152+
; CHECK-NEXT: vsetivli zero, 2, e16alt, mf4, ta, ma
153153
; CHECK-NEXT: vfmacc.vf v8, fa0, v9
154154
; CHECK-NEXT: ret
155155
%head = insertelement <2 x bfloat> poison, bfloat %c, i32 0
@@ -161,7 +161,7 @@ define <2 x bfloat> @vfmacc_vf_v2bf16(<2 x bfloat> %va, <2 x bfloat> %vb, bfloat
161161
define <4 x bfloat> @vfmacc_vv_v4bf16(<4 x bfloat> %va, <4 x bfloat> %vb, <4 x bfloat> %vc) {
162162
; CHECK-LABEL: vfmacc_vv_v4bf16:
163163
; CHECK: # %bb.0:
164-
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
164+
; CHECK-NEXT: vsetivli zero, 4, e16alt, mf2, ta, ma
165165
; CHECK-NEXT: vfmacc.vv v8, v10, v9
166166
; CHECK-NEXT: ret
167167
%vd = call <4 x bfloat> @llvm.fma.v4bf16(<4 x bfloat> %vb, <4 x bfloat> %vc, <4 x bfloat> %va)
@@ -171,7 +171,7 @@ define <4 x bfloat> @vfmacc_vv_v4bf16(<4 x bfloat> %va, <4 x bfloat> %vb, <4 x b
171171
define <4 x bfloat> @vfmacc_vf_v4bf16(<4 x bfloat> %va, <4 x bfloat> %vb, bfloat %c) {
172172
; CHECK-LABEL: vfmacc_vf_v4bf16:
173173
; CHECK: # %bb.0:
174-
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
174+
; CHECK-NEXT: vsetivli zero, 4, e16alt, mf2, ta, ma
175175
; CHECK-NEXT: vfmacc.vf v8, fa0, v9
176176
; CHECK-NEXT: ret
177177
%head = insertelement <4 x bfloat> poison, bfloat %c, i32 0
@@ -183,7 +183,7 @@ define <4 x bfloat> @vfmacc_vf_v4bf16(<4 x bfloat> %va, <4 x bfloat> %vb, bfloat
183183
define <8 x bfloat> @vfmacc_vv_v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, <8 x bfloat> %vc) {
184184
; CHECK-LABEL: vfmacc_vv_v8bf16:
185185
; CHECK: # %bb.0:
186-
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
186+
; CHECK-NEXT: vsetivli zero, 8, e16alt, m1, ta, ma
187187
; CHECK-NEXT: vfmacc.vv v8, v10, v9
188188
; CHECK-NEXT: ret
189189
%vd = call <8 x bfloat> @llvm.fma.v8bf16(<8 x bfloat> %vb, <8 x bfloat> %vc, <8 x bfloat> %va)
@@ -193,7 +193,7 @@ define <8 x bfloat> @vfmacc_vv_v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, <8 x b
193193
define <8 x bfloat> @vfmacc_vf_v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, bfloat %c) {
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; CHECK-LABEL: vfmacc_vf_v8bf16:
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; CHECK: # %bb.0:
196-
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
196+
; CHECK-NEXT: vsetivli zero, 8, e16alt, m1, ta, ma
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; CHECK-NEXT: vfmacc.vf v8, fa0, v9
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; CHECK-NEXT: ret
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%head = insertelement <8 x bfloat> poison, bfloat %c, i32 0
@@ -205,7 +205,7 @@ define <8 x bfloat> @vfmacc_vf_v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, bfloat
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define <16 x bfloat> @vfmacc_vv_v16bf16(<16 x bfloat> %va, <16 x bfloat> %vb, <16 x bfloat> %vc) {
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; CHECK-LABEL: vfmacc_vv_v16bf16:
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; CHECK: # %bb.0:
208-
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
208+
; CHECK-NEXT: vsetivli zero, 16, e16alt, m2, ta, ma
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; CHECK-NEXT: vfmacc.vv v8, v12, v10
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; CHECK-NEXT: ret
211211
%vd = call <16 x bfloat> @llvm.fma.v16bf16(<16 x bfloat> %vb, <16 x bfloat> %vc, <16 x bfloat> %va)
@@ -215,7 +215,7 @@ define <16 x bfloat> @vfmacc_vv_v16bf16(<16 x bfloat> %va, <16 x bfloat> %vb, <1
215215
define <16 x bfloat> @vfmacc_vf_v16bf16(<16 x bfloat> %va, <16 x bfloat> %vb, bfloat %c) {
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; CHECK-LABEL: vfmacc_vf_v16bf16:
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; CHECK: # %bb.0:
218-
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
218+
; CHECK-NEXT: vsetivli zero, 16, e16alt, m2, ta, ma
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; CHECK-NEXT: vfmacc.vf v8, fa0, v10
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; CHECK-NEXT: ret
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%head = insertelement <16 x bfloat> poison, bfloat %c, i32 0

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