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[AArch64] Align ZCM/ZCZ test strictness(NFC) (#200645)
1 parent 013b335 commit 09a709a

5 files changed

Lines changed: 54 additions & 54 deletions

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‎llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmove-fpr.ll‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,12 @@
1-
; RUN: llc < %s -mtriple=arm64-linux-gnu | FileCheck %s -check-prefixes=CHECK,NOZCM-FPR128-CPU --match-full-lines
2-
; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=generic | FileCheck %s -check-prefixes=CHECK,NOZCM-FPR128-CPU --match-full-lines
3-
; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m1 | FileCheck %s -check-prefixes=CHECK,ZCM-FPR128-CPU --match-full-lines
4-
; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m1 -mattr=-zcm-fpr128 | FileCheck %s -check-prefixes=CHECK,NOZCM-FPR128-ATTR --match-full-lines
5-
; RUN: llc < %s -mtriple=arm64-apple-macosx -mattr=+zcm-fpr128 | FileCheck %s -check-prefixes=CHECK,ZCM-FPR128-ATTR --match-full-lines
1+
; RUN: llc < %s -mtriple=arm64-linux-gnu | FileCheck %s --match-full-lines -check-prefixes=CHECK,NOZCM-FPR128-CPU
2+
; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=generic | FileCheck %s --match-full-lines -check-prefixes=CHECK,NOZCM-FPR128-CPU
3+
; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m1 | FileCheck %s --match-full-lines -check-prefixes=CHECK,ZCM-FPR128-CPU
4+
; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m1 -mattr=-zcm-fpr128 | FileCheck %s --match-full-lines -check-prefixes=CHECK,NOZCM-FPR128-ATTR
5+
; RUN: llc < %s -mtriple=arm64-apple-macosx -mattr=+zcm-fpr128 | FileCheck %s --match-full-lines -check-prefixes=CHECK,ZCM-FPR128-ATTR
66

77
define void @zero_cycle_regmove_FPR64(double %a, double %b, double %c, double %d) {
88
entry:
9-
; CHECK-LABEL: {{_?zero_cycle_regmove_FPR64}}:{{ *}}{{(;|//)}}{{ *}}@zero_cycle_regmove_FPR64
9+
; CHECK-LABEL: {{_?zero_cycle_regmove_FPR64}}:{{ *(;|//) *}}@zero_cycle_regmove_FPR64
1010

1111
; NOZCM-FPR128-CPU: fmov d0, d2
1212
; NOZCM-FPR128-CPU: fmov d1, d3
@@ -48,7 +48,7 @@ declare float @foo_double(double, double)
4848

4949
define void @zero_cycle_regmove_FPR32(float %a, float %b, float %c, float %d) {
5050
entry:
51-
; CHECK-LABEL: {{_?zero_cycle_regmove_FPR32}}:{{ *}}{{(;|//)}}{{ *}}@zero_cycle_regmove_FPR32
51+
; CHECK-LABEL: {{_?zero_cycle_regmove_FPR32}}:{{ *(;|//) *}}@zero_cycle_regmove_FPR32
5252

5353
; NOZCM-FPR128-CPU: fmov s0, s2
5454
; NOZCM-FPR128-CPU: fmov s1, s3
@@ -90,7 +90,7 @@ declare float @foo_float(float, float)
9090

9191
define void @zero_cycle_regmove_FPR16(half %a, half %b, half %c, half %d) {
9292
entry:
93-
; CHECK-LABEL: {{_?zero_cycle_regmove_FPR16}}:{{ *}}{{(;|//)}}{{ *}}@zero_cycle_regmove_FPR16
93+
; CHECK-LABEL: {{_?zero_cycle_regmove_FPR16}}:{{ *(;|//) *}}@zero_cycle_regmove_FPR16
9494

9595
; NOZCM-FPR128-CPU: fmov s0, s2
9696
; NOZCM-FPR128-CPU: fmov s1, s3

‎llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmove-fpr8.mir‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
1-
# RUN: llc -o - -run-pass=postrapseudos -mtriple=arm64-linux-gnu %s | FileCheck %s -check-prefixes=ALL,NOZCM-FPR128-CPU --match-full-lines
2-
# RUN: llc -o - -run-pass=postrapseudos -mtriple=arm64-apple-macosx -mcpu=generic %s | FileCheck %s -check-prefixes=ALL,NOZCM-FPR128-CPU --match-full-lines
3-
# RUN: llc -o - -run-pass=postrapseudos -mtriple=arm64-apple-macosx -mcpu=apple-m1 %s | FileCheck %s -check-prefixes=ALL,ZCM-FPR128-CPU --match-full-lines
4-
# RUN: llc -o - -run-pass=postrapseudos -mtriple=arm64-apple-macosx -mcpu=apple-m1 -mattr=-zcm-fpr128 %s | FileCheck %s -check-prefixes=ALL,NOZCM-FPR128-ATTR --match-full-lines
5-
# RUN: llc -o - -run-pass=postrapseudos -mtriple=arm64-apple-macosx -mattr=+zcm-fpr128 %s | FileCheck %s -check-prefixes=ALL,ZCM-FPR128-ATTR --match-full-lines
1+
# RUN: llc -o - -run-pass=postrapseudos -mtriple=arm64-linux-gnu %s | FileCheck %s --match-full-lines -check-prefixes=ALL,NOZCM-FPR128-CPU
2+
# RUN: llc -o - -run-pass=postrapseudos -mtriple=arm64-apple-macosx -mcpu=generic %s | FileCheck %s --match-full-lines -check-prefixes=ALL,NOZCM-FPR128-CPU
3+
# RUN: llc -o - -run-pass=postrapseudos -mtriple=arm64-apple-macosx -mcpu=apple-m1 %s | FileCheck %s --match-full-lines -check-prefixes=ALL,ZCM-FPR128-CPU
4+
# RUN: llc -o - -run-pass=postrapseudos -mtriple=arm64-apple-macosx -mcpu=apple-m1 -mattr=-zcm-fpr128 %s | FileCheck %s --match-full-lines -check-prefixes=ALL,NOZCM-FPR128-ATTR
5+
# RUN: llc -o - -run-pass=postrapseudos -mtriple=arm64-apple-macosx -mattr=+zcm-fpr128 %s | FileCheck %s --match-full-lines -check-prefixes=ALL,ZCM-FPR128-ATTR
66

77
---
88
name: zero_cycle_regmove_FPR8

‎llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmove-gpr.ll‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,12 @@
1-
; RUN: llc < %s -mtriple=arm64-linux-gnu | FileCheck %s -check-prefixes=ALL,NOTCPU-LINUX
2-
; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=generic | FileCheck %s -check-prefixes=ALL,NOTCPU-APPLE
3-
; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m1 | FileCheck %s -check-prefixes=ALL,CPU
4-
; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m1 -mattr=-zcm-gpr64 | FileCheck %s -check-prefixes=ALL,NOTATTR
5-
; RUN: llc < %s -mtriple=arm64-apple-macosx -mattr=+zcm-gpr64 | FileCheck %s -check-prefixes=ALL,ATTR
1+
; RUN: llc < %s -mtriple=arm64-linux-gnu | FileCheck %s --match-full-lines -check-prefixes=ALL,NOTCPU-LINUX
2+
; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=generic | FileCheck %s --match-full-lines -check-prefixes=ALL,NOTCPU-APPLE
3+
; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m1 | FileCheck %s --match-full-lines -check-prefixes=ALL,CPU
4+
; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m1 -mattr=-zcm-gpr64 | FileCheck %s --match-full-lines -check-prefixes=ALL,NOTATTR
5+
; RUN: llc < %s -mtriple=arm64-apple-macosx -mattr=+zcm-gpr64 | FileCheck %s --match-full-lines -check-prefixes=ALL,ATTR
66

77
define void @zero_cycle_regmove_GPR32(i32 %a, i32 %b, i32 %c, i32 %d) {
88
entry:
9-
; ALL-LABEL: {{_?zero_cycle_regmove_GPR32}}:{{ *}}{{(;|//)}}{{ *}}@zero_cycle_regmove_GPR32
9+
; ALL-LABEL: {{_?zero_cycle_regmove_GPR32}}:{{ *(;|//) *}}@zero_cycle_regmove_GPR32
1010

1111
; NOTCPU-LINUX: mov w0, w2
1212
; NOTCPU-LINUX: mov w1, w3

‎llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-fpr.ll‎

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@
1111

1212
define half @tf16() {
1313
entry:
14-
; ALL-LABEL: {{_?}}tf16:{{ *}}{{(;|//)}}{{ *}}@tf16
14+
; ALL-LABEL: {{_?}}tf16:{{ *(;|//) *}}@tf16
1515
; FP-WORKAROUND: fmov s0, wzr
1616
; NOZCZ-FPR64-NOZCZ-FPR128: fmov s0, wzr
1717
; NOZCZ-FPR64-NOZCZ-FPR128-FULLFP16: fmov h0, wzr
@@ -22,7 +22,7 @@ entry:
2222

2323
define float @tf32() {
2424
entry:
25-
; ALL-LABEL: {{_?}}tf32:{{ *}}{{(;|//)}}{{ *}}@tf32
25+
; ALL-LABEL: {{_?}}tf32:{{ *(;|//) *}}@tf32
2626
; FP-WORKAROUND: fmov s0, wzr
2727
; NOZCZ-FPR64-NOZCZ-FPR128: fmov s0, wzr
2828
; ZCZ-FPR64: movi d0, #0000000000000000
@@ -32,7 +32,7 @@ entry:
3232

3333
define double @td64() {
3434
entry:
35-
; ALL-LABEL: {{_?}}td64:{{ *}}{{(;|//)}}{{ *}}@td64
35+
; ALL-LABEL: {{_?}}td64:{{ *(;|//) *}}@td64
3636
; FP-WORKAROUND: fmov d0, xzr
3737
; NOZCZ-FPR64-NOZCZ-FPR128: fmov d0, xzr
3838
; ZCZ-FPR64: movi d0, #0000000000000000
@@ -42,7 +42,7 @@ entry:
4242

4343
define <8 x i8> @tv8i8() {
4444
entry:
45-
; ALL-LABEL: {{_?}}tv8i8:{{ *}}{{(;|//)}}{{ *}}@tv8i8
45+
; ALL-LABEL: {{_?}}tv8i8:{{ *(;|//) *}}@tv8i8
4646
; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0
4747
; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
4848
; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
@@ -52,7 +52,7 @@ entry:
5252

5353
define <4 x i16> @tv4i16() {
5454
entry:
55-
; ALL-LABEL: {{_?}}tv4i16:{{ *}}{{(;|//)}}{{ *}}@tv4i16
55+
; ALL-LABEL: {{_?}}tv4i16:{{ *(;|//) *}}@tv4i16
5656
; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0
5757
; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
5858
; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
@@ -62,7 +62,7 @@ entry:
6262

6363
define <2 x i32> @tv2i32() {
6464
entry:
65-
; ALL-LABEL: {{_?}}tv2i32:{{ *}}{{(;|//)}}{{ *}}@tv2i32
65+
; ALL-LABEL: {{_?}}tv2i32:{{ *(;|//) *}}@tv2i32
6666
; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0
6767
; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
6868
; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
@@ -72,7 +72,7 @@ entry:
7272

7373
define <2 x float> @tv2f32() {
7474
entry:
75-
; ALL-LABEL: {{_?}}tv2f32:{{ *}}{{(;|//)}}{{ *}}@tv2f32
75+
; ALL-LABEL: {{_?}}tv2f32:{{ *(;|//) *}}@tv2f32
7676
; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0
7777
; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
7878
; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
@@ -82,7 +82,7 @@ entry:
8282

8383
define <16 x i8> @tv16i8() {
8484
entry:
85-
; ALL-LABEL: {{_?}}tv16i8:{{ *}}{{(;|//)}}{{ *}}@tv16i8
85+
; ALL-LABEL: {{_?}}tv16i8:{{ *(;|//) *}}@tv16i8
8686
; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0
8787
; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
8888
; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
@@ -92,7 +92,7 @@ entry:
9292

9393
define <8 x i16> @tv8i16() {
9494
entry:
95-
; ALL-LABEL: {{_?}}tv8i16:{{ *}}{{(;|//)}}{{ *}}@tv8i16
95+
; ALL-LABEL: {{_?}}tv8i16:{{ *(;|//) *}}@tv8i16
9696
; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0
9797
; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
9898
; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
@@ -102,7 +102,7 @@ entry:
102102

103103
define <4 x i32> @tv4i32() {
104104
entry:
105-
; ALL-LABEL: {{_?}}tv4i32:{{ *}}{{(;|//)}}{{ *}}@tv4i32
105+
; ALL-LABEL: {{_?}}tv4i32:{{ *(;|//) *}}@tv4i32
106106
; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0
107107
; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
108108
; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
@@ -112,7 +112,7 @@ entry:
112112

113113
define <2 x i64> @tv2i64() {
114114
entry:
115-
; ALL-LABEL: {{_?}}tv2i64:{{ *}}{{(;|//)}}{{ *}}@tv2i64
115+
; ALL-LABEL: {{_?}}tv2i64:{{ *(;|//) *}}@tv2i64
116116
; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0
117117
; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
118118
; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
@@ -122,7 +122,7 @@ entry:
122122

123123
define <4 x float> @tv4f32() {
124124
entry:
125-
; ALL-LABEL: {{_?}}tv4f32:{{ *}}{{(;|//)}}{{ *}}@tv4f32
125+
; ALL-LABEL: {{_?}}tv4f32:{{ *(;|//) *}}@tv4f32
126126
; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0
127127
; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
128128
; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
@@ -132,7 +132,7 @@ entry:
132132

133133
define <2 x double> @tv2d64() {
134134
entry:
135-
; ALL-LABEL: {{_?}}tv2d64:{{ *}}{{(;|//)}}{{ *}}@tv2d64
135+
; ALL-LABEL: {{_?}}tv2d64:{{ *(;|//) *}}@tv2d64
136136
; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0
137137
; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
138138
; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
@@ -142,7 +142,7 @@ entry:
142142

143143
; We used to produce spills+reloads for a Q register with zero cycle zeroing
144144
; enabled.
145-
; ALL-LABEL: {{_?}}foo:{{ *}}{{(;|//)}}{{ *}}@foo
145+
; ALL-LABEL: {{_?}}foo:{{ *(;|//) *}}@foo
146146
; ALL-NOT: str q{{[0-9]+}}
147147
; ALL-NOT: ldr q{{[0-9]+}}
148148
define double @foo(i32 %n) {

‎llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-gpr.ll‎

Lines changed: 21 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -1,44 +1,44 @@
1-
; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s -check-prefixes=ALL,NOZCZ-GPR32-NOZCZ-GPR64
2-
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+zcz-gpr32 | FileCheck %s -check-prefixes=ALL,ZCZ-GPR32
3-
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+zcz-gpr64 | FileCheck %s -check-prefixes=ALL,NOZCZ-GPR32-ZCZ-GPR64
4-
; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=generic | FileCheck %s -check-prefixes=ALL,NOZCZ-GPR32-NOZCZ-GPR64
5-
; RUN: llc < %s -mtriple=arm64-apple-ios -mcpu=cyclone | FileCheck %s -check-prefixes=ALL,ZCZ-GPR32,ZCZ-GPR64
6-
; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m1 | FileCheck %s -check-prefixes=ALL,ZCZ-GPR32,ZCZ-GPR64
7-
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=exynos-m3 | FileCheck %s -check-prefixes=ALL,NOZCZ-GPR32-NOZCZ-GPR64
8-
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=kryo | FileCheck %s -check-prefixes=ALL,ZCZ-GPR32,ZCZ-GPR64
9-
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=falkor | FileCheck %s -check-prefixes=ALL,ZCZ-GPR32,ZCZ-GPR64
1+
; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s --match-full-lines -check-prefixes=ALL,NOZCZ-GPR32-NOZCZ-GPR64
2+
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+zcz-gpr32 | FileCheck %s --match-full-lines -check-prefixes=ALL,ZCZ-GPR32
3+
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+zcz-gpr64 | FileCheck %s --match-full-lines -check-prefixes=ALL,NOZCZ-GPR32-ZCZ-GPR64
4+
; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=generic | FileCheck %s --match-full-lines -check-prefixes=ALL,NOZCZ-GPR32-NOZCZ-GPR64
5+
; RUN: llc < %s -mtriple=arm64-apple-ios -mcpu=cyclone | FileCheck %s --match-full-lines -check-prefixes=ALL,ZCZ-GPR32,ZCZ-GPR64
6+
; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m1 | FileCheck %s --match-full-lines -check-prefixes=ALL,ZCZ-GPR32,ZCZ-GPR64
7+
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=exynos-m3 | FileCheck %s --match-full-lines -check-prefixes=ALL,NOZCZ-GPR32-NOZCZ-GPR64
8+
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=kryo | FileCheck %s --match-full-lines -check-prefixes=ALL,ZCZ-GPR32,ZCZ-GPR64
9+
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=falkor | FileCheck %s --match-full-lines -check-prefixes=ALL,ZCZ-GPR32,ZCZ-GPR64
1010

1111
define i8 @ti8() {
1212
entry:
13-
; ALL-LABEL: ti8:
13+
; ALL-LABEL: {{_?}}ti8:{{ *(;|//) *}}@ti8
1414
; NOZCZ-GPR32-NOZCZ-GPR64: mov w0, wzr
15-
; ZCZ-GPR32: mov w0, #0
16-
; NOZCZ-GPR32-ZCZ-GPR64: mov x0, #0
15+
; ZCZ-GPR32: mov w0, #0{{ *(;|//) *}}=0x0
16+
; NOZCZ-GPR32-ZCZ-GPR64: mov x0, #0{{ *(;|//) *}}=0x0
1717
ret i8 0
1818
}
1919

2020
define i16 @ti16() {
2121
entry:
22-
; ALL-LABEL: ti16:
22+
; ALL-LABEL: {{_?}}ti16:{{ *(;|//) *}}@ti16
2323
; NOZCZ-GPR32-NOZCZ-GPR64: mov w0, wzr
24-
; ZCZ-GPR32: mov w0, #0
25-
; NOZCZ-GPR32-ZCZ-GPR64: mov x0, #0
24+
; ZCZ-GPR32: mov w0, #0{{ *(;|//) *}}=0x0
25+
; NOZCZ-GPR32-ZCZ-GPR64: mov x0, #0{{ *(;|//) *}}=0x0
2626
ret i16 0
2727
}
2828

2929
define i32 @ti32() {
3030
entry:
31-
; ALL-LABEL: ti32:
31+
; ALL-LABEL: {{_?}}ti32:{{ *(;|//) *}}@ti32
3232
; NOZCZ-GPR32-NOZCZ-GPR64: mov w0, wzr
33-
; ZCZ-GPR32: mov w0, #0
34-
; NOZCZ-GPR32-ZCZ-GPR64: mov x0, #0
33+
; ZCZ-GPR32: mov w0, #0{{ *(;|//) *}}=0x0
34+
; NOZCZ-GPR32-ZCZ-GPR64: mov x0, #0{{ *(;|//) *}}=0x0
3535
ret i32 0
3636
}
3737

3838
define i64 @ti64() {
3939
entry:
40-
; ALL-LABEL: ti64:
41-
; NOZCZ-GPR32-NOZCZ-GPR64 mov x0, xzr
42-
; ZCZ-GPR64: mov x0, #0
40+
; ALL-LABEL: {{_?}}ti64:{{ *(;|//) *}}@ti64
41+
; NOZCZ-GPR32-NOZCZ-GPR64: mov x0, xzr
42+
; ZCZ-GPR64: mov x0, #0{{ *(;|//) *}}=0x0
4343
ret i64 0
4444
}

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