Systems & High-Performance Computing Engineer · IIIT Sonepat
Compilers, reconfigurable hardware, and distributed systems — working at the layer where algorithms meet silicon.
- System Software Research Intern @ C-DAC Bengaluru — compiler & runtime development for CGRAs (Coarse-Grained Reconfigurable Architectures), Verilog RTL
- IEEE-published researcher — signal processing (quaternion transforms, speech/dysarthria detection), edge AI
- Founding Chair, IEEE Student Branch @ IIIT Sonepat
Compiler & Hardware
- End-to-end CGRA compiler architecture implementation — modulo scheduling, parametric Verilog RTL, synthesis via Yosys/Icarus Verilog
- Research into GPU driver/runtime internals and memory isolation
Distributed Systems & Backend
- Distributed Task Orchestrator — Go, gRPC, Redis
- Autonomous SRE Copilot — Go backend, automated incident response
Systems & Infrastructure
- Driver validation suite tooling, GitLab Runner CI/CD (built from source on Fedora)
- QEMU/KVM-based virtualization work
- Discrete implementation of Quaternion Linear Canonical Transform — IEEE Signal Processing Letters
Indian Institute of Information Technology (IIIT), Sonepat B.Tech in Computer Science and Engineering (2023 — 2027)
"Understand it down to the transistor, then build upward."