Halide feature names for AVX512 don't match commonly-used abbreviations #6651
Description
We use names that are (presumably) based on the specific microarchitecture where a feature was first introduced (e.g. avx512_sapphirerapids), but the apparently-standard extensions are much terser and more granular, e.g. from https://en.wikichip.org/wiki/x86/avx-512:
AVX512F - [AVX-512 Foundation](https://en.wikichip.org/w/index.php?title=x86/avx512f&action=edit&redlink=1) is base of the 512-bit SIMD instruction extensions which is a comprehensive list of features for most HPC and enterprise applications. AVX-512 Foundation is the natural extensions to AVX/AVX2 which is extended using the [EVEX](https://en.wikichip.org/w/index.php?title=x86/evex&action=edit&redlink=1) prefix which builds on the existing [VEX](https://en.wikichip.org/w/index.php?title=x86/vex&action=edit&redlink=1) prefix. Any processor that implements any portion of the AVX-512 extensions MUST implement AVX512F.
AVX512CD - [AVX-512 Conflict Detection](https://en.wikichip.org/w/index.php?title=x86/avx512cd&action=edit&redlink=1) Instructions offer additional vectorization of loops with possible address conflict.
AVX512DQ - [AVX-512 Doubleword and Quadword](https://en.wikichip.org/w/index.php?title=x86/avx512dq&action=edit&redlink=1) Instructions add new 32-bit and 64-bit AVX-512 instructions (conversion, transcendental support, etc..).
AVX512PF - [AVX-512 Prefetch](https://en.wikichip.org/w/index.php?title=x86/avx512pf&action=edit&redlink=1) Instructions add new prefetch instructions for gather/scatter and PREFETCHWT1 .
AVX512ER - [AVX-512 Exponential and Reciprocal](https://en.wikichip.org/w/index.php?title=x86/avx512er&action=edit&redlink=1) Instructions (ERI) offer 28-bit precision RCP, RSQRT and EXP transcendentals for various scientific applications.
AVX512VL - [AVX-512 Vector Length](https://en.wikichip.org/w/index.php?title=x86/avx512vl&action=edit&redlink=1) Instructions add vector length orthogonality, allowing most AVX-512 operations to also operate on [XMM](https://en.wikichip.org/w/index.php?title=x86/xmm&action=edit&redlink=1) (128-bit [SSE](https://en.wikichip.org/w/index.php?title=x86/sse&action=edit&redlink=1)) registers and [YMM](https://en.wikichip.org/w/index.php?title=x86/ymm&action=edit&redlink=1) (256-bit [AVX](https://en.wikichip.org/w/index.php?title=x86/avx&action=edit&redlink=1)) registers
AVX512BW - [AVX-512 Byte and Word](https://en.wikichip.org/w/index.php?title=x86/avx512bw&action=edit&redlink=1) Instructions add support for for 8-bit and 16-bit integer operations.
AVX512IFMA - [AVX-512 Integer Fused Multiply-Add](https://en.wikichip.org/w/index.php?title=x86/avx512ifma&action=edit&redlink=1) Instructions add support for fused multiply add of integers using 52-bit precision.
AVX512VBMI - [AVX-512 Vector Bit Manipulation, Version 1](https://en.wikichip.org/w/index.php?title=x86/avx512vbmi&action=edit&redlink=1) add additional vector byte permutation instructions.
AVX512VBMI2 - [AVX-512 Vector Bit Manipulation, Version 2](https://en.wikichip.org/w/index.php?title=x86/avx512vbmi2&action=edit&redlink=1) add additional vector byte permutation instructions.
AVX512VAES - [AVX-512 Vector AES](https://en.wikichip.org/w/index.php?title=x86/avx512vaes&action=edit&redlink=1) Instructions add vector AES operations
AVX512BITALG - [AVX-512 Bit Algorithms](https://en.wikichip.org/w/index.php?title=x86/avx512bitalg&action=edit&redlink=1) add bit algorithms operations
AVX5124FMAPS - [AVX-512 Fused Multiply Accumulation Packed Single precision](https://en.wikichip.org/w/index.php?title=x86/avx512_4fmaps&action=edit&redlink=1) Instructions add vector instructions for deep learning on floating-point single precision
AVX512VPCLMULQDQ - [AVX-512 Vector Carry-less Multiply](https://en.wikichip.org/w/index.php?title=x86/avx512vpclmulqdq&action=edit&redlink=1) add vector carry-less multiply operations
AVX512GFNI - [AVX-512 Galois Field New Instructions](https://en.wikichip.org/w/index.php?title=x86/avx512gfni&action=edit&redlink=1) add Galois Field transformations instructions
AVX512_VNNI - [AVX-512 Vector Neural Network Instructions](https://en.wikichip.org/wiki/x86/avx512_vnni) add vector instructions for deep learning
AVX5124VNNIW - [AVX-512 Vector Neural Network Instructions Word Variable Precision](https://en.wikichip.org/w/index.php?title=x86/avx512_4vnniw&action=edit&redlink=1) Instructions add vector instructions for deep learning on enhanced word variable precision
AVX512VPOPCNTDQ - [AVX-512 Vector Population Count Doubleword and Quadword](https://en.wikichip.org/w/index.php?title=x86/avx512_vpopcntdq&action=edit&redlink=1) Instructions add double and quad word population count instructions.
AVX512_BF16 - [AVX-512 BFloat16 Instructions](https://en.wikichip.org/wiki/x86/avx512_bf16) add vector instructions for operating on [bfloat16](https://en.wikichip.org/wiki/bfloat16)
Seems like moving to the standard nomenclature here would be greatly preferable for ease of interop and cognitive load. (We'd want to keep-but-deprecate the existing features until next Halide release, of course.)