cpu: add Int8 matrix multiplication instructions CPU feature flag for ARM64

hmartinez82 · gopherbot · commit 7bb0bf703bd3 · 2024-07-17T17:57:00.000Z
References: https://github.com/torvalds/linux/blob/5bbd9b249880dba032bffa002dd9cd12cd5af09c/arch/arm64/include/uapi/asm/hwcap.h#L75C9-L75C31 https://developer.arm.com/documentation/ddi0601/2024-03/AArch64-Registers/ID-AA64ISAR1-EL1--AArch64-Instruction-Set-Attribute-Register-1 Change-Id: Ic4e1cf2c23097c7e8695453b6d0b335756d474bc Reviewed-on: https://go-review.googlesource.com/c/sys/+/595678 Reviewed-by: Ian Lance Taylor <iant@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Auto-Submit: Ian Lance Taylor <iant@golang.org> Reviewed-by: Cherry Mui <cherryyz@google.com>
diff --git a/cpu/cpu.go b/cpu/cpu.go
@@ -106,6 +106,7 @@ var ARM64 struct {
 	HasSVE2     bool // Scalable Vector Extensions 2
 	HasASIMDFHM bool // Advanced SIMD multiplication FP16 to FP32
 	HasDIT      bool // Data Independent Timing support
+	HasI8MM     bool // Advanced SIMD Int8 matrix multiplication instructions
 	_           CacheLinePad
 }
 
diff --git a/cpu/cpu_arm64.go b/cpu/cpu_arm64.go
@@ -39,6 +39,7 @@ func initOptions() {
 		{Name: "asimddp", Feature: &ARM64.HasASIMDDP},
 		{Name: "asimdfhm", Feature: &ARM64.HasASIMDFHM},
 		{Name: "dit", Feature: &ARM64.HasDIT},
+		{Name: "i8mm", Feature: &ARM64.HasI8MM},
 	}
 }
 
@@ -146,6 +147,11 @@ func parseARM64SystemRegisters(isar0, isar1, pfr0 uint64) {
 		ARM64.HasLRCPC = true
 	}
 
+	switch extractBits(isar1, 52, 55) {
+	case 1:
+		ARM64.HasI8MM = true
+	}
+
 	// ID_AA64PFR0_EL1
 	switch extractBits(pfr0, 16, 19) {
 	case 0:
diff --git a/cpu/cpu_linux_arm64.go b/cpu/cpu_linux_arm64.go
@@ -38,6 +38,7 @@ const (
 	hwcap_DIT      = 1 << 24
 
 	hwcap2_SVE2 = 1 << 1
+	hwcap2_I8MM = 1 << 13
 )
 
 // linuxKernelCanEmulateCPUID reports whether we're running
@@ -112,6 +113,7 @@ func doinit() {
 
 	// HWCAP2 feature bits
 	ARM64.HasSVE2 = isSet(hwCap2, hwcap2_SVE2)
+	ARM64.HasI8MM = isSet(hwCap2, hwcap2_I8MM)
 }
 
 func isSet(hwc uint, value uint) bool {

Original file line number	Diff line number	Diff line change
`@@ -106,6 +106,7 @@ var ARM64 struct {`
`106`	`106`	`HasSVE2 bool // Scalable Vector Extensions 2`
`107`	`107`	`HasASIMDFHM bool // Advanced SIMD multiplication FP16 to FP32`
`108`	`108`	`HasDIT bool // Data Independent Timing support`
	`109`	`+ HasI8MM bool // Advanced SIMD Int8 matrix multiplication instructions`
`109`	`110`	`_ CacheLinePad`
`110`	`111`	`}`
`111`	`112`
Original file line number	Diff line number	Diff line change
`@@ -39,6 +39,7 @@ func initOptions() {`
`39`	`39`	`{Name: "asimddp", Feature: &ARM64.HasASIMDDP},`
`40`	`40`	`{Name: "asimdfhm", Feature: &ARM64.HasASIMDFHM},`
`41`	`41`	`{Name: "dit", Feature: &ARM64.HasDIT},`
	`42`	`+ {Name: "i8mm", Feature: &ARM64.HasI8MM},`
`42`	`43`	`}`
`43`	`44`	`}`
`44`	`45`
`@@ -146,6 +147,11 @@ func parseARM64SystemRegisters(isar0, isar1, pfr0 uint64) {`
`146`	`147`	`ARM64.HasLRCPC = true`
`147`	`148`	`}`
`148`	`149`
	`150`	`+ switch extractBits(isar1, 52, 55) {`
	`151`	`+ case 1:`
	`152`	`+ ARM64.HasI8MM = true`
	`153`	`+ }`
	`154`	`+`
`149`	`155`	`// ID_AA64PFR0_EL1`
`150`	`156`	`switch extractBits(pfr0, 16, 19) {`
`151`	`157`	`case 0:`
Original file line number	Diff line number	Diff line change
`@@ -38,6 +38,7 @@ const (`
`38`	`38`	`hwcap_DIT = 1 << 24`
`39`	`39`
`40`	`40`	`hwcap2_SVE2 = 1 << 1`
	`41`	`+ hwcap2_I8MM = 1 << 13`
`41`	`42`	`)`
`42`	`43`
`43`	`44`	`// linuxKernelCanEmulateCPUID reports whether we're running`
`@@ -112,6 +113,7 @@ func doinit() {`
`112`	`113`
`113`	`114`	`// HWCAP2 feature bits`
`114`	`115`	`ARM64.HasSVE2 = isSet(hwCap2, hwcap2_SVE2)`
	`116`	`+ ARM64.HasI8MM = isSet(hwCap2, hwcap2_I8MM)`
`115`	`117`	`}`
`116`	`118`
`117`	`119`	`func isSet(hwc uint, value uint) bool {`