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cpu: add support for detecting RISC-V extensions
Add a RISCV64 variable to cpu that indicates both the presence of RISC-V extensions and performance information about the underlying RISC-V cores. The variable is only populated with non false values on Linux. The detection code first attempts to use the riscv_hwprobe syscall introduced in Linux 6.4, falling back to HWCAP if riscv_hwprobe is not supported. The patch can detect the C, V, Zba, Zbb and Zbs extensions. V, Zba, Zbb and Zbs can only be detected on a 6.5 kernel or later (without backports). Updates golang/go#61416 Change-Id: I40f92724ee3d337c06bdc559ff0b18a8f6bfda9f Reviewed-on: https://go-review.googlesource.com/c/sys/+/605815 Reviewed-by: Cherry Mui <[email protected]> Reviewed-by: Dmitri Shuralyov <[email protected]> LUCI-TryBot-Result: Go LUCI <[email protected]> Reviewed-by: Joel Sing <[email protected]> Reviewed-by: Meng Zhuo <[email protected]>
1 parent 29e55b2 commit 3283fc3

5 files changed

+175
-2
lines changed

‎cpu/cpu.go

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@@ -201,6 +201,25 @@ var S390X struct {
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_ CacheLinePad
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}
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// RISCV64 contains the supported CPU features and performance characteristics for riscv64
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// platforms. The booleans in RISCV64, with the exception of HasFastMisaligned, indicate
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// the presence of RISC-V extensions.
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//
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// It is safe to assume that all the RV64G extensions are supported and so they are omitted from
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// this structure. As riscv64 Go programs require at least RV64G, the code that populates
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// this structure cannot run successfully if some of the RV64G extensions are missing.
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// The struct is padded to avoid false sharing.
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var RISCV64 struct {
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_ CacheLinePad
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HasFastMisaligned bool // Fast misaligned accesses
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HasC bool // Compressed instruction-set extension
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HasV bool // Vector extension compatible with RVV 1.0
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HasZba bool // Address generation instructions extension
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HasZbb bool // Basic bit-manipulation extension
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HasZbs bool // Single-bit instructions extension
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_ CacheLinePad
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}
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func init() {
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archInit()
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initOptions()

‎cpu/cpu_linux_noinit.go

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@@ -2,7 +2,7 @@
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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5-
//go:build linux && !arm && !arm64 && !mips64 && !mips64le && !ppc64 && !ppc64le && !s390x
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//go:build linux && !arm && !arm64 && !mips64 && !mips64le && !ppc64 && !ppc64le && !s390x && !riscv64
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package cpu
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‎cpu/cpu_linux_riscv64.go

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@@ -0,0 +1,137 @@
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// Copyright 2024 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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package cpu
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import (
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"syscall"
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"unsafe"
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)
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// RISC-V extension discovery code for Linux. The approach here is to first try the riscv_hwprobe
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// syscall falling back to HWCAP to check for the C extension if riscv_hwprobe is not available.
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//
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// A note on detection of the Vector extension using HWCAP.
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//
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// Support for the Vector extension version 1.0 was added to the Linux kernel in release 6.5.
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// Support for the riscv_hwprobe syscall was added in 6.4. It follows that if the riscv_hwprobe
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// syscall is not available then neither is the Vector extension (which needs kernel support).
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// The riscv_hwprobe syscall should then be all we need to detect the Vector extension.
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// However, some RISC-V board manufacturers ship boards with an older kernel on top of which
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// they have back-ported various versions of the Vector extension patches but not the riscv_hwprobe
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// patches. These kernels advertise support for the Vector extension using HWCAP. Falling
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// back to HWCAP to detect the Vector extension, if riscv_hwprobe is not available, or simply not
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// bothering with riscv_hwprobe at all and just using HWCAP may then seem like an attractive option.
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//
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// Unfortunately, simply checking the 'V' bit in AT_HWCAP will not work as this bit is used by
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// RISC-V board and cloud instance providers to mean different things. The Lichee Pi 4A board
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// and the Scaleway RV1 cloud instances use the 'V' bit to advertise their support for the unratified
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// 0.7.1 version of the Vector Specification. The Banana Pi BPI-F3 and the CanMV-K230 board use
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// it to advertise support for 1.0 of the Vector extension. Versions 0.7.1 and 1.0 of the Vector
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// extension are binary incompatible. HWCAP can then not be used in isolation to populate the
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// HasV field as this field indicates that the underlying CPU is compatible with RVV 1.0.
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//
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// There is a way at runtime to distinguish between versions 0.7.1 and 1.0 of the Vector
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// specification by issuing a RVV 1.0 vsetvli instruction and checking the vill bit of the vtype
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// register. This check would allow us to safely detect version 1.0 of the Vector extension
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// with HWCAP, if riscv_hwprobe were not available. However, the check cannot
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// be added until the assembler supports the Vector instructions.
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//
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// Note the riscv_hwprobe syscall does not suffer from these ambiguities by design as all of the
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// extensions it advertises support for are explicitly versioned. It's also worth noting that
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// the riscv_hwprobe syscall is the only way to detect multi-letter RISC-V extensions, e.g., Zba.
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// These cannot be detected using HWCAP and so riscv_hwprobe must be used to detect the majority
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// of RISC-V extensions.
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//
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// Please see https://docs.kernel.org/arch/riscv/hwprobe.html for more information.
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// golang.org/x/sys/cpu is not allowed to depend on golang.org/x/sys/unix so we must
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// reproduce the constants, types and functions needed to make the riscv_hwprobe syscall
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// here.
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const (
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// Copied from golang.org/x/sys/unix/ztypes_linux_riscv64.go.
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riscv_HWPROBE_KEY_IMA_EXT_0 = 0x4
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riscv_HWPROBE_IMA_C = 0x2
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riscv_HWPROBE_IMA_V = 0x4
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riscv_HWPROBE_EXT_ZBA = 0x8
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riscv_HWPROBE_EXT_ZBB = 0x10
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riscv_HWPROBE_EXT_ZBS = 0x20
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riscv_HWPROBE_KEY_CPUPERF_0 = 0x5
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riscv_HWPROBE_MISALIGNED_FAST = 0x3
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riscv_HWPROBE_MISALIGNED_MASK = 0x7
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)
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const (
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// sys_RISCV_HWPROBE is copied from golang.org/x/sys/unix/zsysnum_linux_riscv64.go.
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sys_RISCV_HWPROBE = 258
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)
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// riscvHWProbePairs is copied from golang.org/x/sys/unix/ztypes_linux_riscv64.go.
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type riscvHWProbePairs struct {
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key int64
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value uint64
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}
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const (
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// CPU features
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hwcap_RISCV_ISA_C = 1 << ('C' - 'A')
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)
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func doinit() {
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// A slice of key/value pair structures is passed to the RISCVHWProbe syscall. The key
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// field should be initialised with one of the key constants defined above, e.g.,
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// RISCV_HWPROBE_KEY_IMA_EXT_0. The syscall will set the value field to the appropriate value.
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// If the kernel does not recognise a key it will set the key field to -1 and the value field to 0.
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pairs := []riscvHWProbePairs{
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{riscv_HWPROBE_KEY_IMA_EXT_0, 0},
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{riscv_HWPROBE_KEY_CPUPERF_0, 0},
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}
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// This call only indicates that extensions are supported if they are implemented on all cores.
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if riscvHWProbe(pairs, 0) {
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if pairs[0].key != -1 {
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v := uint(pairs[0].value)
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RISCV64.HasC = isSet(v, riscv_HWPROBE_IMA_C)
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RISCV64.HasV = isSet(v, riscv_HWPROBE_IMA_V)
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RISCV64.HasZba = isSet(v, riscv_HWPROBE_EXT_ZBA)
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RISCV64.HasZbb = isSet(v, riscv_HWPROBE_EXT_ZBB)
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RISCV64.HasZbs = isSet(v, riscv_HWPROBE_EXT_ZBS)
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}
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if pairs[1].key != -1 {
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v := pairs[1].value & riscv_HWPROBE_MISALIGNED_MASK
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RISCV64.HasFastMisaligned = v == riscv_HWPROBE_MISALIGNED_FAST
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}
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}
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// Let's double check with HWCAP if the C extension does not appear to be supported.
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// This may happen if we're running on a kernel older than 6.4.
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if !RISCV64.HasC {
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RISCV64.HasC = isSet(hwCap, hwcap_RISCV_ISA_C)
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}
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}
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func isSet(hwc uint, value uint) bool {
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return hwc&value != 0
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}
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// riscvHWProbe is a simplified version of the generated wrapper function found in
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// golang.org/x/sys/unix/zsyscall_linux_riscv64.go. We simplify it by removing the
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// cpuCount and cpus parameters which we do not need. We always want to pass 0 for
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// these parameters here so the kernel only reports the extensions that are present
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// on all cores.
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func riscvHWProbe(pairs []riscvHWProbePairs, flags uint) bool {
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var _zero uintptr
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var p0 unsafe.Pointer
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if len(pairs) > 0 {
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p0 = unsafe.Pointer(&pairs[0])
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} else {
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p0 = unsafe.Pointer(&_zero)
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}
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_, _, e1 := syscall.Syscall6(sys_RISCV_HWPROBE, uintptr(p0), uintptr(len(pairs)), uintptr(0), uintptr(0), uintptr(flags), 0)
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return e1 == 0
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}

‎cpu/cpu_riscv64.go

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@@ -8,4 +8,13 @@ package cpu
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const cacheLineSize = 64
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11-
func initOptions() {}
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func initOptions() {
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options = []option{
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{Name: "fastmisaligned", Feature: &RISCV64.HasFastMisaligned},
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{Name: "c", Feature: &RISCV64.HasC},
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{Name: "v", Feature: &RISCV64.HasV},
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{Name: "zba", Feature: &RISCV64.HasZba},
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{Name: "zbb", Feature: &RISCV64.HasZbb},
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{Name: "zbs", Feature: &RISCV64.HasZbs},
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}
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}

‎cpu/cpu_test.go

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@@ -61,6 +61,14 @@ func TestMIPS64Initialized(t *testing.T) {
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}
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}
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func TestRISCV64Initialized(t *testing.T) {
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if runtime.GOARCH == "riscv64" {
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if !cpu.Initialized {
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t.Fatal("Initialized expected true, got false")
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}
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}
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}
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// On ppc64x, the ISA bit for POWER8 should always be set on POWER8 and beyond.
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func TestPPC64minimalFeatures(t *testing.T) {
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// Do not run this with gccgo on ppc64, as it doesn't have POWER8 as a minimum

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