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cherrymuicherrymui
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Revert "cmd/compile: enable address folding for global symbols of shared library"
This reverts CL 445535. Reason for revert: see issue #58826. It doesn't handle large offset well. Fixes #58826. Change-Id: Ic4a33f4c510c88628ea7e16207a60977a04cf798 Reviewed-on: https://go-review.googlesource.com/c/go/+/474175 Reviewed-by: Heschi Kreinick <[email protected]> TryBot-Result: Gopher Robot <[email protected]> Run-TryBot: Cherry Mui <[email protected]> Reviewed-by: Keith Randall <[email protected]>
1 parent c80b991 commit a4cf4fd

2 files changed

Lines changed: 209 additions & 132 deletions

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‎src/cmd/compile/internal/ssa/_gen/ARM64.rules‎

Lines changed: 88 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -838,25 +838,35 @@
838838
(MOVDaddr [int32(off1)+off2] {sym} ptr)
839839

840840
// fold address into load/store
841-
(MOVBload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) =>
841+
(MOVBload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
842+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
842843
(MOVBload [off1+int32(off2)] {sym} ptr mem)
843-
(MOVBUload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) =>
844+
(MOVBUload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
845+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
844846
(MOVBUload [off1+int32(off2)] {sym} ptr mem)
845-
(MOVHload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) =>
847+
(MOVHload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
848+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
846849
(MOVHload [off1+int32(off2)] {sym} ptr mem)
847-
(MOVHUload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) =>
850+
(MOVHUload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
851+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
848852
(MOVHUload [off1+int32(off2)] {sym} ptr mem)
849-
(MOVWload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) =>
853+
(MOVWload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
854+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
850855
(MOVWload [off1+int32(off2)] {sym} ptr mem)
851-
(MOVWUload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) =>
856+
(MOVWUload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
857+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
852858
(MOVWUload [off1+int32(off2)] {sym} ptr mem)
853-
(MOVDload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) =>
859+
(MOVDload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
860+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
854861
(MOVDload [off1+int32(off2)] {sym} ptr mem)
855-
(LDP [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) =>
862+
(LDP [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
863+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
856864
(LDP [off1+int32(off2)] {sym} ptr mem)
857-
(FMOVSload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) =>
865+
(FMOVSload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
866+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
858867
(FMOVSload [off1+int32(off2)] {sym} ptr mem)
859-
(FMOVDload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) =>
868+
(FMOVDload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
869+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
860870
(FMOVDload [off1+int32(off2)] {sym} ptr mem)
861871

862872
// register indexed load
@@ -921,29 +931,41 @@
921931
(FMOVDloadidx8 ptr (MOVDconst [c]) mem) && is32Bit(c<<3) => (FMOVDload ptr [int32(c)<<3] mem)
922932
(FMOVSloadidx4 ptr (MOVDconst [c]) mem) && is32Bit(c<<2) => (FMOVSload ptr [int32(c)<<2] mem)
923933

924-
(MOVBstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) =>
934+
(MOVBstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2)
935+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
925936
(MOVBstore [off1+int32(off2)] {sym} ptr val mem)
926-
(MOVHstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) =>
937+
(MOVHstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2)
938+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
927939
(MOVHstore [off1+int32(off2)] {sym} ptr val mem)
928-
(MOVWstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) =>
940+
(MOVWstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2)
941+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
929942
(MOVWstore [off1+int32(off2)] {sym} ptr val mem)
930-
(MOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) =>
943+
(MOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2)
944+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
931945
(MOVDstore [off1+int32(off2)] {sym} ptr val mem)
932-
(STP [off1] {sym} (ADDconst [off2] ptr) val1 val2 mem) && is32Bit(int64(off1)+off2) =>
946+
(STP [off1] {sym} (ADDconst [off2] ptr) val1 val2 mem) && is32Bit(int64(off1)+off2)
947+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
933948
(STP [off1+int32(off2)] {sym} ptr val1 val2 mem)
934-
(FMOVSstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) =>
949+
(FMOVSstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2)
950+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
935951
(FMOVSstore [off1+int32(off2)] {sym} ptr val mem)
936-
(FMOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) =>
952+
(FMOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2)
953+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
937954
(FMOVDstore [off1+int32(off2)] {sym} ptr val mem)
938-
(MOVBstorezero [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) =>
955+
(MOVBstorezero [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
956+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
939957
(MOVBstorezero [off1+int32(off2)] {sym} ptr mem)
940-
(MOVHstorezero [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) =>
958+
(MOVHstorezero [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
959+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
941960
(MOVHstorezero [off1+int32(off2)] {sym} ptr mem)
942-
(MOVWstorezero [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) =>
961+
(MOVWstorezero [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
962+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
943963
(MOVWstorezero [off1+int32(off2)] {sym} ptr mem)
944-
(MOVDstorezero [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) =>
964+
(MOVDstorezero [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
965+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
945966
(MOVDstorezero [off1+int32(off2)] {sym} ptr mem)
946-
(MOVQstorezero [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) =>
967+
(MOVQstorezero [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
968+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
947969
(MOVQstorezero [off1+int32(off2)] {sym} ptr mem)
948970

949971
// register indexed store
@@ -992,71 +1014,93 @@
9921014
(FMOVSstoreidx4 ptr (MOVDconst [c]) val mem) && is32Bit(c<<2) => (FMOVSstore [int32(c)<<2] ptr val mem)
9931015

9941016
(MOVBload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
995-
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
1017+
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
1018+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
9961019
(MOVBload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
9971020
(MOVBUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
998-
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
1021+
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
1022+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
9991023
(MOVBUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
10001024
(MOVHload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
1001-
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
1025+
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
1026+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
10021027
(MOVHload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
10031028
(MOVHUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
1004-
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
1029+
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
1030+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
10051031
(MOVHUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
10061032
(MOVWload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
1007-
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
1033+
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
1034+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
10081035
(MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
10091036
(MOVWUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
1010-
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
1037+
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
1038+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
10111039
(MOVWUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
10121040
(MOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
1013-
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
1041+
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
1042+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
10141043
(MOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
10151044
(LDP [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
1016-
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
1045+
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
1046+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
10171047
(LDP [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
10181048
(FMOVSload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
1019-
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
1049+
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
1050+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
10201051
(FMOVSload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
10211052
(FMOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
1022-
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
1053+
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
1054+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
10231055
(FMOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
10241056

10251057
(MOVBstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
1026-
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
1058+
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
1059+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
10271060
(MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
10281061
(MOVHstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
1029-
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
1062+
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
1063+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
10301064
(MOVHstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
10311065
(MOVWstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
1032-
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
1066+
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
1067+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
10331068
(MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
10341069
(MOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
1035-
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
1070+
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
1071+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
10361072
(MOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
10371073
(STP [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val1 val2 mem)
1038-
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
1074+
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
1075+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
10391076
(STP [off1+off2] {mergeSym(sym1,sym2)} ptr val1 val2 mem)
10401077
(FMOVSstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
1041-
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
1078+
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
1079+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
10421080
(FMOVSstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
10431081
(FMOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
1044-
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
1082+
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
1083+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
10451084
(FMOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
10461085
(MOVBstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
1047-
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
1086+
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
1087+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
10481088
(MOVBstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
10491089
(MOVHstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
1050-
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
1090+
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
1091+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
10511092
(MOVHstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
10521093
(MOVWstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
1053-
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
1094+
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
1095+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
10541096
(MOVWstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
10551097
(MOVDstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
1056-
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
1098+
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
1099+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
10571100
(MOVDstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
10581101
(MOVQstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
1059-
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
1102+
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
1103+
&& (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
10601104
(MOVQstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
10611105

10621106
// store zero

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