Details:
- PR flame#738 -- which moved -fPIC flag insertion responsibilities from
  common.mk to the subconfigs' individual make_defs.mk files -- was 
  merged shortly before the introduction of new RISC-V subconfigs in 
  flame#693. This commit brings those RISC-V subconfigs up to date with the 
  new -fPIC conventions.

Details:
- This commit fixes issue #746, in which the _access() function (called
  from within blastest/f2c/open.c) is undeclared when compiling on
  Windows with clang 16.
- (cherry picked from commit ef9d3e6)

Fix bug in detecting Fortran compiler vendor (#745)

`FC` was used instead of `found_fc`.
- (cherry picked from 6fd9aab)

Apply #738 to make_defs.mk of RISC-V subconfigs. (#740)

Details:
- PR #738 -- which moved -fPIC flag insertion responsibilities from
  common.mk to the subconfigs' individual make_defs.mk files -- was
  merged shortly before the introduction of new RISC-V subconfigs in
  #693. This commit brings those RISC-V subconfigs up to date with the
  new -fPIC conventions.
- (cherry picked from 8215b02)

Add RISC-V target (#693)

Details:
- There are four RISC-V base configurations: 'rv32i', 'rv32iv', 'rv64i',
  and 'rv64iv', namely the 32-bit and 64-bit implementations with and
  without the 'V' vector extension. Additional extensions such as 'M'
  (multiplication), 'A' (atomics), 'F' ('float' hardware support), 'D'
  ('double' hardware support), and 'C' (compressed-length instructions),
  are automatically used when available. If they are not available, then
  software equivalents (e.g., softfloat and -latomic) are used.
- './configure auto' can be invoked on a RISC-V build platform, and will
  automatically detect RISC-V CPU extensions through the RISC-V C API:
  https://github.com/riscv-non-isa/riscv-c-api-doc/blob/master/riscv-c-api.md
- The assembly kernels assume the presence of the vector extension
  RVV 1.0.
- It is possible to build 'rv[32,64]iv' for any value of VLEN.
  However, if VLEN < 128, the targets will fall back to the generic
  kernels and blocksizes.
- The vector microkernels are vector-length agnostic and work with
  every VLEN >=128, but are expected to work best with smaller vector
  lengths, i.e., VLEN <= 512.
- The assembly kernels cover column major storage (rs_c == 1).
- The blocksizes aim at being a good generic choice for out-of-order
  cores. They are not tuned to a specific RISC-V HPC core.
- The vector kernels have been tested using vlen={128,256,512}.
- The single- and double-precision assembly code routines for 'sgemm'
  and 'dgemm', or for 'cgemm' and 'zgemm', are combined in their RISC-V
  vector assembly source code, and are differentiated only with macros.
- The XLEN=32 and XLEN=64 versions of the RISC-V assembly code are
  identical, except that callee-saved registers are saved and restored
  differently. There are RISC-V assembly code #include files for
  handling the saving and restoring of callee-saved registers, and they
  are future-proof if ever XLEN=128.
- Multiplications, such as computing array strides and offsets, are
  performed in C, and later passed to the RISC-V assembly kernels. This
  is so that the compiler can determine whether the 'M' (multiply)
  extension is available and use multiplication instructions, or call
  library helper functions instead.
- A new macro called bli_static_assert() has been added to perform
  static assertions at compile-time, regardless of the C/C++ dialect of
  the compiler. The original motivation of this was to ensure that
  calling RISC-V assembly kernels would not silently truncate arguments
  of type 'dim_t' or 'inc_t' (so-called "narrowing conversions").
- RISC-V CI tests have been added to Travis CI, using the
  riscv-gnu-toolchain cross-compiler, and qemu simulator.
- Thanks to Lee Killough for collaborating on this commit.
- (cherry picked from 6b38c5a)