By aarch64, could you provide some details about the exact type of cpu / soc this patch has been benchmarked on ?

Hi, @Cyan4973 , the result have been benchmarked on the Arm N1/A72/A57 platforms and observed similar uplift.

I can't remember why this code was added here.

It could be that, with aarch64 being merely an instruction set under which so many different SoCs are built, maybe some of them (non N1) would prefer the first loop.
However, it's pretty hard to confirm / test (couldn't find a test platform where this holds true).

From what I can see, the second formulation just separates the first branch from later ones, so that it can have its own statistics (as opposed to being merged with other loop iterations). Such a construction is expected to be rather good in the context of wildcopy, essentially distinguishing small copies from larger ones. This should translate into almost always better performance, except maybe for specific systems with rather poor branch predictors.

So I'm gonna make an educated guess here and state that this PR seems tends to improve the situation, on top of simplifying it by removing a weird and poorly documented corner case.

Thank you @Cyan4973 for the review. I used to check the log info of that change (969ba4f), but could not find the context of it. It looks like this is designed for compression. With my benchmarks here, I didn't find regression in compression with removing the aarch64 specific part on N1/A72/A57.

Thanks for the PR @JunHe77!