LiteX can create SoCs with or without CPU. Some simple SoCs don’t use any CPU (bridging SoCs for example), some SoCs use a CPU but external to the FPGA (PCIe SoCs for example where the CPU is directly the CPU of the Host machine) but in most of the cases the SoC embedded a "Soft CPU" to control the system and/or ease splitting tasks between software/hardware.

The authoritative CPU list is the LiteX CPU registry, built from the wrappers in:

litex/soc/cores/cpu/*/core.py

The currently registered CPU types can also be inspected from a LiteX checkout with:

python3 -c "from litex.soc.cores.cpu import CPUS; print('\n'.join(sorted(str(k) for k in CPUS if k is not None)))"

--cpu-type=None is also supported for SoCs without an embedded CPU.

Currently the supported Soft CPUs are:

• blackparrot -- BlackParrot, a 64-bit Linux-capable accelerator host multicore that implements the rv64imafdc instruction set.
• coreblocks -- a RISC-V soft core.
• cortex_m1 -- an ARM Cortex-M1 soft core.
• cortex_m3 -- an ARM Cortex-M3 soft core.
• cv32e40p -- a CORE-V 32-bit RISC-V soft core.
• cv32e41p -- a CORE-V 32-bit RISC-V soft core.
• cva5 -- a 32-bit RISC-V soft core.
• cva6 -- a configurable RISC-V soft core.
• fazyrv -- a 32-bit RISC-V soft core.
• femtorv -- a small 32-bit RISC-V soft core.
• firev -- a 32-bit RISC-V soft core.
• ibex -- a 32-bit RISC-V soft core.
• kianv -- a 32-bit RISC-V soft core.
• lm32 -- a LatticeMico32 soft core.
• marocchino -- an OpenRISC soft core.
• microwatt -- a PowerPC soft core.
• minerva -- a CPU core that currently implements the RISC-V RV32I instruction set with its microarchitecture described in plain Python code using the nMigen toolbox.
• mor1kx -- an OpenRISC 1000 soft core (see also Open RISC on Wikipedia).
• naxriscv -- a RISC-V soft core.
• neorv32 -- NEORV32, a small, platform-agnostic and highly extendable 32-bit RTOS-capable RISC-V core.
• openc906 -- a RISC-V soft core.
• picorv32 -- a Small RISC V core by Clifford Wolf, implementing the rv32imc instruction set (or configured subsets).
• rocket -- Rocket Chip, a configurable, fully featured, 64-bit rv64imafdc capable core.
• sentinel -- a 32-bit RISC-V soft core.
• serv -- a small 32-bit RISC-V soft core.
• urv -- a 32-bit RISC-V soft core.
• vexiiriscv -- an FPGA-friendly RISC-V soft core by SpinalHDL.
• vexriscv -- an FPGA Friendly RISC V core by SpinalHDL, implementing the rv32im instruction set (hardware multiply optional).
• vexriscv_smp -- a Linux-capable SMP VexRiscv configuration.

Most of these CPUs have multiple configuration variants which customize the configuration to target a specific type of firmware, performance and resource usage. All these CPUs can be used with your own bare metal firmware.

Variant names are CPU-specific, so the same variant name does not always imply the exact same micro-architecture or feature set on every CPU. The lists below summarize common variants; the CPU wrappers remain the authoritative source for exact support.

Aliases: min

Minimal is the smallest possible working configuration for a given CPU type. These features frequently disables a large number of useful such as illegal instruction exceptions and similar. It should only be used if the absolute smallest configuration is needed.

• cva5
• lm32
• neorv32
• picorv32
• vexriscv

Aliases: zephyr, nuttx, light

Lite is the configuration which should work okay for bare metal firmware and RTOS like NuttX or Zephyr on small big FPGAs like the Lattice iCE40 parts. It can also be used for designs which are more resource constrained.

• Lattice iCE40 Series - iCE40HX, iCE40LP, iCE40UP5K
• Any resource constrained design.

• lm32
• neorv32
• vexriscv

Aliases: std

Standard is the default configuration which should work well for bare metal firmware and RTOS like NuttX or Zephyr on modern big FPGAs.

• blackparrot
• coreblocks
• cortex_m1
• cortex_m3
• cv32e40p
• cv32e41p
• cva5
• cva6
• fazyrv
• femtorv
• firev
• ibex
• kianv
• lm32
• marocchino
• microwatt
• minerva
• mor1kx
• naxriscv
• neorv32
• openc906
• picorv32
• rocket
• sentinel
• serv
• urv
• vexiiriscv
• vexriscv
• vexriscv_smp

• Xilinx 7-Series - Artix7, Kintex7, Spartan7
• Xilinx Spartan6
• Lattice ECP5

This target enables all features of each CPU.

• coreblocks
• cva6
• neorv32
• rocket
• vexriscv

This target enables CPU features such as MMU that are required to get Linux booting.

• coreblocks (small_linux)
• marocchino
• mor1kx
• rocket
• vexiiriscv
• vexriscv
• vexriscv_smp

Extensions are added to the CPU variant with a +. For example a minimal variant with the debug extension would be minimal+debug.

The debug extension enables extra features useful for debugging. This normally includes things like JTAG port.

• neorv32
• vexriscv

The mmu extension enables a memory protection unit.

• mor1kx
• vexriscv

The hmul extension enables hardware multiplication acceleration.

The fpu extension enables a floating point acceleration unit.

• cv32e40p
• mor1kx

• lm32 support was added to upstream GCC around ~2009, no clang support.
• or1k support was added to upstream GCC in version 9.0.0, clang support was added upstream in version XXX
• riscv support (VexRiscv, PicoRV32, Minerva, Rocket and others) was added to upstream GCC in version 7.1.0, clang support was added upstream in version 3.1

You can compile your own compiler, download a precompiled toolchain, install a RISC-V toolchain with litex_setup.py, or use an environment like TimVideos LiteX BuildEnv which provides precompiled toolchain for all three architectures.

Note: RISC-V toolchains support or require various extensions. Generally rv32i is used on smaller FPGAs, and rv32im on larger FPGAs -- the rv32im adds hardware multiplication and division (see RISC V ISA base and extensions on Wikipedia for more detail).

The notes below provide extra background for some common soft CPUs. They are not intended to be an exhaustive list of all CPU wrappers; use the summary above or the LiteX CPU registry for the current complete list.

LatticeMico32 soft core, small and designed for an FPGA.

• minimal
• lite
• standard

• Upstream GCC
• Upstream Binutils

• No upstream Linux, very old Linux port
• Upstream NuttX
• No Zephyr support

• No current new activity

An OpenRISC 1000 soft core (see also Open RISC on Wikipedia).

• standard
• standard+fpu
• linux
• linux+fpu
• linux+smp
• linux+smp+fpu

• Upstream GCC
• Upstream Binutils
• Upstream clang

• No Zephyr support
• No NuttX support
• Upstream Linux

• Reasonable amount of activity.

A FPGA Friendly RISC V core by SpinalHDL, implementing the rv32im instruction set (hardware multiply optional).

• minimal
• minimal+debug
• minimal+debug+hwbp
• lite
• lite+debug
• lite+debug+hwbp
• standard
• standard+debug
• imac
• imac+debug
• full
• full+cfu
• full+debug
• full+cfu+debug
• linux
• linux+debug
• linux+no-dsp
• secure
• secure+debug

• Upstream GCC
• Upstream Binutils
• Upstream clang

• Upstream Zephyr
• Unknown NuttX support
• Upstream Linux (in progress)

• Lots of current activity
• Currently supported under both LiteX & MiSoC

A small RISC V core by Clifford Wolf, implementing the rv32imc instruction set (or configured subsets).

• minimal
• standard

• Upstream GCC
• Upstream Binutils
• Upstream clang

• Out of tree Zephyr
• Unknown NuttX support
• Too small for Linux

• Some activity

The Minerva is a CPU core that currently implements the RISC-V RV32I instruction set with its microarchitecture described in plain Python code using the nMigen toolbox.

• standard

• Upstream GCC
• Upstream Binutils
• Upstream clang

• Unknown Zephyr support
• Unknown NuttX support
• Unknown Linux support

• Some activity

The Rocket Chip is a full-featured, configurable CPU core that implements up to the full RISC-V RV64IMAFDC (a.k.a. RV64GC) instruction set, with its microarchitecture described in Chisel.

• small
• medium
• linux (rv64imac with enabled hardware MMU)
• full (rv64imafdc with enabled hardware MMU and FPU)

• Upstream GCC
• Upstream Binutils
• Upstream clang

• Full upstream Linux support (for models with MMU enabled)

• Lots of activity
• Reference design for several taped-out ASICs (e.g., from SiFive)

The NEORV32 RISC-V Processor is a tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

• minimal (rv32i_Zicsr_Zifencei)
• minimal+debug
• lite (rv32imc_Zicsr_Zifencei)
• lite+debug
• standard (rv32imc_Zicsr_Zifencei_Zicntr + i-cache, fast MUL (DSPs) and barrel-shifter)
• standard+debug
• full (rv32imcu_Zicsr_Zifencei_Zicntr_Zihpm + i-cache + physical memory protection, fast MUL (DSPs) and barrel-shifter)
• full+debug
• numa
• numa+debug

• Upstream GCC
• Upstream Binutils
• Upstream openOCD and GDB

• Upstream Zephyr support
• FreeRTOS port

• gitter channel
• community-driven example setups and projects for various FPGAs, boards and toolchains