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@github-actions github-actions bot commented Sep 11, 2021

Backport of #58914 to release/6.0

/cc @BruceForstall

Customer Impact

On Windows/x86, on machines without SSE41 available, certain calls to functions returning a Vector2 type (8-byte SIMD type) will generate bad code and corrupt the function return value.

Testing

Running the previously failing repro case, SuperPMI asm diffs, normal CI testing.

Risk

Very low.

On Windows/x86, if a call returns a SIMD8 in two registers
(eax, edx), and needs to be assembled and stored into a single
SIMD register, AND we don't have the SSE41 ABI available (because
the hardware doesn't support it, or we specifically disable it),
then we need a temporary register. In the failure case, the target
register and temporary register were the same, and then interfered
with each other. The fix is to force the temporary register to
be different from the target register.

Fixes #58899
@ghost ghost added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Sep 11, 2021
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ghost commented Sep 11, 2021

Tagging subscribers to this area: @JulieLeeMSFT
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Issue Details

Backport of #58914 to release/6.0

/cc @BruceForstall

Customer Impact

Testing

Risk

Author: github-actions[bot]
Assignees: -
Labels:

area-CodeGen-coreclr

Milestone: -

@BruceForstall
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@kunalspathak @dotnet/jit-contrib PTAL: backport of very simple fix

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LGTM

@BruceForstall
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@jeffschwMSFT PTAL

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Approved

@jeffschwMSFT jeffschwMSFT merged commit d6a35f3 into release/6.0 Sep 13, 2021
@jkotas jkotas deleted the backport/pr-58914-to-release/6.0 branch September 18, 2021 04:09
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4 participants