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@imhameed imhameed commented Jan 15, 2021

This change:

  • Unpacks SIMD parameters passed via multiple GPRs (LLVMArgVtypeAsIArgs) into
    local LLVM SSA vector-typed values on function entry. The calling convention we
    use on arm and arm64 has "large" value types passed in multiple GPRs when
    possible, and the way this is currently encoded in the LLVM IR we emit is by
    using parameters with the LLVM type [Size x {i32 or i64}], where the
    resulting size of this type, in bytes, is at least as large as the size of the
    value type encoded within.

  • Packs SIMD return values into multiple GPRs (LLVMArgVtypeAsScalar); the way
    this is currently encoded in the LLVM IR we emit for arm64 (but not arm) is by
    using a "wide" LLVM integer type (e.g. i128).

  • Makes OP_LDADDR aware of our special-case handling of SIMD value types:
    SIMD value types passed via an indirection (LLVMArgVtypeAddr or
    LLVMArgVtypeByRef) are loaded from memory to an LLVM SSA value in the initial
    basic block, but OP_LDADDR had previously assumed that any value type passed
    via an indirection had an associated LLVM SSA value containing an indirection
    rather than the actual value.

  • Adds a debugging utility function (mono_llvm_dump_type).

  • Gives greppable names to some allocas.

  • Makes some formerly amd64-specific SIMD-related opcodes also work on arm64.

This code is all a bit messy (especially the parts surrounding parameter
passing); this change does not clean any of this up.

@imhameed imhameed changed the title Add basic Vector128 support for arm64. [mono] Add basic Vector128 support for arm64. Jan 15, 2021
@imhameed imhameed force-pushed the llvm-arm64-vector_t branch 3 times, most recently from 73d4d40 to 56d198c Compare January 15, 2021 09:02
SIMD value types are preemptively loaded from LLVM IR memory into an
LLVM IR value in the initial basic block, but OP_LDADDR wasn't aware of
this, and assumed that the LLVM value associated with the argument's
vreg was the argument's address.
In the ABI we use on arm and arm64, value types can be passed in and out
of function calls in multiple GPRs. For function parameters on both arm
and arm64, this is done by encoding the parameter as an LLVM array of
machine-register-sized elements that has a byte length at least as large
as the value type being passed. Converting this array to a SIMD vector
in the initial BB ensures that `addresses [vreg]` and `values [vreg]`
have consistent types.
@imhameed imhameed force-pushed the llvm-arm64-vector_t branch from e3da617 to 20b3523 Compare January 20, 2021 03:22
@imhameed imhameed marked this pull request as ready for review January 20, 2021 04:13
@imhameed imhameed merged commit 8c76312 into dotnet:master Jan 20, 2021
@ghost ghost locked as resolved and limited conversation to collaborators Feb 19, 2021
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3 participants