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@echesakov echesakov commented Nov 25, 2020

Backport of #45225 to release/5.0

Customer Impact

Apple Silicon with Rosetta 2 emulation uses a 16K memory page. This configuration sends the runtime into untested and unstable stack probing configuration which causes crashes in Rosetta 2 emulation. We need this fixed to support Apple Silicon.

Regression

No. Apple Silicon is a new scenario which we are backporting to .NET 5

Testing

  • Applied change to 5.0 tip. Ran full set of priority 1 tests on Apple Silicon under Rosetta 2 emulation. All symptoms of stack issues were resolved.

Risk

This is a low risk change. It changes stack probing to use a constant 4k page size. This is the industry standard minimum page size used across all supported CPU architectures. The use of a constant reduces complexity and simplifies testing. Fixes issues with mismatched AOT and runtime page sizes.

@dotnet/jit-contrib
cc @sdmaclea

@echesakov echesakov added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Nov 25, 2020
@echesakov echesakov added this to the 5.0.x milestone Nov 25, 2020
@echesakov echesakov self-assigned this Nov 25, 2020
@sdmaclea
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sdmaclea commented Dec 1, 2020

Apple has indicated this issue only affects the Apple Silicon DTK and is fixed on M1 commercial hardware running under Rosetta. Closing this PR.

@sdmaclea sdmaclea closed this Dec 1, 2020
@ghost ghost locked as resolved and limited conversation to collaborators Dec 31, 2020
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