JIT: fix SIMD12 relocatable-address containment check in ContainCheckIndir - #132676

Lowering::ContainCheckIndir on xarch tested addr->TypeIs(TYP_SIMD12), but addr is the address operand and is always pointer/byref typed — so the condition was vacuously true and the relocation restriction described in the comment right below it never applied.

 #if defined(FEATURE_SIMD)
-        if ((!addr->TypeIs(TYP_SIMD12) || !icon->ImmedValNeedsReloc(m_compiler)) && icon->FitsInAddrBase(m_compiler))
+        if ((!node->TypeIs(TYP_SIMD12) || !icon->ImmedValNeedsReloc(m_compiler)) && icon->FitsInAddrBase(m_compiler))
 #else

The restriction belongs on the indirection's type: genLoadIndTypeSimd12/genStoreIndTypeSimd12 reach the upper element via a second access at +8, which they implement by mutating a contained address constant (icon->SetIconValue(icon->IconValue() + 8)) under assert(!icon->ImmedValNeedsReloc(m_compiler)).

• Scope: only affects compilation with JIT_FLAG_RELOC (AOT). For the runtime JIT ImmedValNeedsReloc is always false, so containment behavior is unchanged there.
• Grep check: this was the only addr->TypeIs(TYP_SIMD12) occurrence in the JIT.

Verification

A NativeAOT compile (checked JIT) of a static Vector3 load/store hits this today:

ILC: Assertion failed '!icon->ImmedValNeedsReloc(m_compiler)' in 'Repro:Store(System.Numerics.Vector3)' during 'Generate code'

With the change the address constant is no longer contained and the upper-element access is correct:

lea       rax, [(reloc 0x4203c8)]
movsd     qword ptr [rax], xmm0
extractps dword ptr [rax+0x08], xmm0, 2

On regression tests

No test added. The path requires AOT relocations, so a JitBlue test cannot reach it; conversely any NativeAOT compilation of a static Vector3 store trips the assert under a checked JIT, so existing NativeAOT legs already cover the class broadly. Happy to add an explicit test under src/tests/nativeaot/ if reviewers prefer one.