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Pull request overview
This PR fixes an ARM64 JIT register allocation bug where LSRA (Linear Scan Register Allocator) fails under JIT register stress when allocating 4 consecutive registers that wrap around from d31 to d0, d1, d2 for SVE VectorTableLookup instructions.
Changes:
- Introduces a helper function
getNextFPRegWraparound()to correctly handle register wraparound from REG_FP_LAST to REG_FP_FIRST - Replaces bit-shift mask calculation with an iterative loop that properly handles the d31→d0 wraparound case
- Consolidates three instances of inline wraparound logic into calls to the new helper function
Reviewed changes
Copilot reviewed 2 out of 2 changed files in this pull request and generated no comments.
| File | Description |
|---|---|
| src/coreclr/jit/lsraarm64.cpp | Adds getNextFPRegWraparound() helper function and replaces the broken bit-shift mask calculation with a loop that correctly builds the consecutiveRegsInUseThisLocation mask by iterating through registers using the wraparound helper |
| src/coreclr/jit/lsra.h | Declares the new getNextFPRegWraparound() helper function in the LinearScan class under the TARGET_ARM64 conditional block |
jakobbotsch
approved these changes
Feb 24, 2026
Co-authored-by: Copilot <[email protected]>
This was referenced Feb 25, 2026
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Running out of consecutive registers for arm64 under jit reg stress. Lsra is trying to place
C380, C381, V363, V364into four consecutive registersd31, d0, d1, d2for a VectorTableLookup (TBL) and runs out of registers when trying to assign V364 asd2.LSRA can normally handle this wraparound. Issue is that the C381 def also occupies d2, so d2 is incorrectly considered not available for V364. Normally this conflict is handled by the
LinearScan::consecutiveRegsInUseThisLocationmask - but the way the mask is calculated does not handle the d31->d0 wraparound properly.fixes #124357