[RISC-V] Substituting INS_ori and INS_addi with INS_mov for zero immediate values#116956
[RISC-V] Substituting INS_ori and INS_addi with INS_mov for zero immediate values#116956jakobbotsch merged 5 commits intodotnet:mainfrom
Conversation
There was a problem hiding this comment.
Pull Request Overview
This PR substitutes 32-bit addi/ori instructions with the 16-bit compressed mv (INS_mov) for zero immediates in RISC-V codegen, reducing native code size.
genSimpleReturnnow emitsINS_movinstead ofINS_addiwhen the immediate is zero.- Several local-heap, cast, and LEA emitters replace
emitIns_R_R_I(..., 0)withemitIns_R_R(INS_mov, ...).
Comments suppressed due to low confidence (1)
src/coreclr/jit/codegenriscv64.cpp:1429
- There are no unit tests verifying that INS_mov is emitted for zero immediates; consider adding codegen tests to ensure mv is generated instead of addi/ori and that code size benefits are validated.
emit->emitIns_R_R(INS_mov, easz, regCnt, targetReg);
|
Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch |
RISC-V Release-CLR-QEMU: 9086 / 9116 (99.67%)report.xml, report.md, failures.xml, testclr_details.tar.zst RISC-V Release-CLR-VF2: 9087 / 9117 (99.67%)report.xml, report.md, failures.xml, testclr_details.tar.zst RISC-V Release-FX-QEMU: 283841 / 284911 (99.62%)report.xml, report.md, failures.xml, testclr_details.tar.zst RISC-V Release-FX-VF2: 510321 / 512066 (99.66%)report.xml, report.md, failures.xml, testclr_details.tar.zst Build information and commandsGIT: |
|
cc @tomeksowi |
RISC-V Release-CLR-QEMU: 9086 / 9116 (99.67%)report.xml, report.md, failures.xml, testclr_details.tar.zst RISC-V Release-CLR-VF2: 9087 / 9117 (99.67%)report.xml, report.md, failures.xml, testclr_details.tar.zst RISC-V Release-FX-QEMU: 275972 / 277043 (99.61%)report.xml, report.md, failures.xml, testclr_details.tar.zst RISC-V Release-FX-VF2: 498288 / 500030 (99.65%)report.xml, report.md, failures.xml, testclr_details.tar.zst Build information and commandsGIT: |
0ac9ad8 to
10a76f3
Compare
RISC-V Release-CLR-VF2: 9087 / 9117 (99.67%)report.xml, report.md, failures.xml, testclr_details.tar.zst Build information and commandsGIT: |
RISC-V Release-FX-QEMU: 283642 / 284660 (99.64%)report.xml, report.md, failures.xml, testclr_details.tar.zst Build information and commandsGIT: |
RISC-V Release-CLR-QEMU: 9086 / 9116 (99.67%)report.xml, report.md, failures.xml, testclr_details.tar.zst Build information and commandsGIT: |
RISC-V Release-FX-QEMU: 283846 / 284916 (99.62%)report.xml, report.md, failures.xml, testclr_details.tar.zst RISC-V Release-CLR-QEMU: 9086 / 9116 (99.67%)report.xml, report.md, failures.xml, testclr_details.tar.zst RISC-V Release-FX-VF2: 305373 / 307123 (99.43%)report.xml, report.md, failures.xml, testclr_details.tar.zst Build information and commandsGIT: |
RISC-V Release-CLR-VF2: 9087 / 9117 (99.67%)report.xml, report.md, failures.xml, testclr_details.tar.zst RISC-V Release-FX-QEMU: 281186 / 282272 (99.62%)report.xml, report.md, failures.xml, testclr_details.tar.zst RISC-V Release-CLR-QEMU: 9086 / 9116 (99.67%)report.xml, report.md, failures.xml, testclr_details.tar.zst Build information and commandsGIT: |
|
@jakobbotsch @jkotas Could you review and merge this PR? This is substituting instructions with RISC-V pseudo instructions for better code readability. Thank you. |
RISC-V Release-CLR-QEMU: 9086 / 9116 (99.67%)report.xml, report.md, failures.xml, testclr_details.tar.zst RISC-V Release-CLR-VF2: 9087 / 9117 (99.67%)report.xml, report.md, failures.xml, testclr_details.tar.zst RISC-V Release-FX-QEMU: 283473 / 284549 (99.62%)report.xml, report.md, failures.xml, testclr_details.tar.zst RISC-V Release-FX-VF2: 308390 / 310083 (99.45%)report.xml, report.md, failures.xml, testclr_details.tar.zst Build information and commandsGIT: |
|
@jakobbotsch Could you merge if there is no problem in this PR? |
|
/ba-g Unrelated failures |
Substituting INS_ori and INS_addi with INS_mov for zero immediate values.
@clamp03 @tomeksowi @SkyShield, @credo-quia-absurdum
part of #84834, cc @dotnet/samsung