ARM64-SVE: Emit AddSequentialAcross correctly
#106292
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ghost
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the
area-CodeGen-coreclr
This was referenced Aug 12, 2024
a74nh
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Aug 13, 2024
| break; | ||
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| // <V><dn>, <Pg>, <V><dn>, <Zm>.<T> | ||
| case IF_SVE_HJ_3A: // ........xx...... ...gggmmmmmddddd -- SVE floating-point serial reduction (predicated) |
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I'm surprised this was never caught in the codegen testing. Although it's possible something else changed around it.
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Yeah, I imagine this was refactored at some point after it was first implemented
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@TIHan can you PTAL? Thanks! |
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@TIHan, @dotnet/arm64-contrib, please review this PR before RC1 snap. |
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LGTM, straightforward change.
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Fixes #106180.
AddSequentialAcrossnow looks like this in JIT disasms:We no longer emit
movprfx, and the destination SIMD register is printed correctly (I think this is everything we needed to fix for this intrinsic). I also found a couple of other nearby instruction formats that needed to be fixed inemitDispInsSveHelp.AddSequentialAcrossstress tests are passing. @dotnet/arm64-contrib PTAL, thanks!