Noticed in #85189, >>> isn't optimized down to AdvSimd.ShiftRightLogical on ARM.
Tanner pointed at
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case NI_Vector64_ShiftLeft: |
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case NI_Vector128_ShiftLeft: |
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{ |
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assert(sig->numArgs == 2); |
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op2 = impPopStack().val; |
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op1 = impSIMDPopStack(); |
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retNode = gtNewSimdBinOpNode(GT_LSH, retType, op1, op2, simdBaseJitType, simdSize); |
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break; |
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} |
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case NI_Vector64_ShiftRightArithmetic: |
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case NI_Vector128_ShiftRightArithmetic: |
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{ |
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assert(sig->numArgs == 2); |
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genTreeOps op = varTypeIsUnsigned(simdBaseType) ? GT_RSZ : GT_RSH; |
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op2 = impPopStack().val; |
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op1 = impSIMDPopStack(); |
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retNode = gtNewSimdBinOpNode(op, retType, op1, op2, simdBaseJitType, simdSize); |
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break; |
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} |
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case NI_Vector64_ShiftRightLogical: |
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case NI_Vector128_ShiftRightLogical: |
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{ |
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assert(sig->numArgs == 2); |
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op2 = impPopStack().val; |
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op1 = impSIMDPopStack(); |
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retNode = gtNewSimdBinOpNode(GT_RSZ, retType, op1, op2, simdBaseJitType, simdSize); |
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break; |
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} |
as the relevant code.
