Ensure XMM16-XMM31 and K0-K7 are handled where appropriate #84087
Description
As part of adding AVX512 and EVEX support, we need to ensure the new registers are supported where required. Outside the places we've already handled, we need to double check the following additional locations...
A few locations are already being handled in #84088
Various debugger related files. src/coreclr/inc/cvconst.h in particular looks to be copy/paste from a file that ships with VS:
src/coreclr/debug/di/amd64/cordbregisterset.cpp:53: | SETBITULONG64( REGISTER_AMD64_XMM15 );
src/coreclr/debug/di/amd64/cordbregisterset.cpp:83: | SETBITULONG64( REGISTER_AMD64_XMM15 ) ) )
src/coreclr/debug/di/amd64/cordbregisterset.cpp:128: ; i<=REGISTER_AMD64_XMM15 && iRegister < regCount
src/coreclr/debug/di/amd64/cordbregisterset.cpp:185: case REGISTER_AMD64_XMM15:
src/coreclr/debug/di/rsthread.cpp:6787: if ((reg >= REGISTER_AMD64_XMM0) && (reg <= REGISTER_AMD64_XMM15))
src/coreclr/debug/di/rsthread.cpp:7034: (index <= REGISTER_AMD64_XMM15)))
src/coreclr/debug/di/shimstackwalk.cpp:21:static const ULONG32 REGISTER_AMD64_MAX = REGISTER_AMD64_XMM15 + 1;
src/coreclr/debug/ee/funceval.cpp:385: case REGISTER_AMD64_XMM15:
src/coreclr/debug/ee/funceval.cpp:601: case REGISTER_AMD64_XMM15:
src/coreclr/debug/inc/dbgtargetcontext.h:267: DT_M128A Xmm15;
src/coreclr/debug/shared/amd64/primitives.cpp:64: // Xmm0-Xmm15
src/coreclr/debug/shared/amd64/primitives.cpp:65: CopyContextChunk(&(pDst->Xmm0), &(pSrc->Xmm0), &(pDst->Xmm15) + 1,
src/coreclr/inc/cordebug.idl:3783: REGISTER_AMD64_XMM15,
src/coreclr/inc/cvconst.h:3190: CV_AMD64_XMM15 = 259,
src/coreclr/inc/cvconst.h:3220: CV_AMD64_XMM15_0 = 288,
src/coreclr/inc/cvconst.h:3221: CV_AMD64_XMM15_1 = 289,
src/coreclr/inc/cvconst.h:3222: CV_AMD64_XMM15_2 = 290,
src/coreclr/inc/cvconst.h:3223: CV_AMD64_XMM15_3 = 291,
src/coreclr/inc/cvconst.h:3232: CV_AMD64_XMM15L = 299,
src/coreclr/inc/cvconst.h:3241: CV_AMD64_XMM15H = 307,
src/coreclr/inc/cvconst.h:3368: CV_AMD64_XMM15IL = 415,
src/coreclr/inc/cvconst.h:3385: CV_AMD64_XMM15IH = 431,
Various NAOT related places (CC. @MichalStrehovsky):
src/coreclr/nativeaot/Runtime/PalRedhawk.h:207: Fp128 Xmm15;
src/coreclr/nativeaot/Runtime/PalRedhawkCommon.h:135: Fp128 Xmm15;
src/coreclr/nativeaot/Runtime/amd64/AsmOffsetsCpu.h:57:PLAT_ASM_OFFSET(0f0, PAL_LIMITED_CONTEXT, Xmm15)
src/coreclr/nativeaot/Runtime/amd64/ExceptionHandling.asm:68: save_xmm128_postrsp Xmm15, rsp_offsetof_Context + OFFSETOF__PAL_LIMITED_CONTEXT__Xmm15
src/coreclr/nativeaot/Runtime/amd64/ExceptionHandling.asm:151: save_xmm128_postrsp Xmm15, rsp_offsetof_Context + OFFSETOF__PAL_LIMITED_CONTEXT__Xmm15
src/coreclr/nativeaot/Runtime/amd64/ExceptionHandling.asm:245: save_xmm128_postrsp Xmm15, rsp_offsetof_Context + OFFSETOF__PAL_LIMITED_CONTEXT__Xmm15
src/coreclr/nativeaot/Runtime/amd64/ExceptionHandling.asm:294: xmm_save_area_size = 10 * 10h ;; xmm6..xmm15 save area
src/coreclr/nativeaot/Runtime/amd64/ExceptionHandling.asm:310: save_xmm128_postrsp xmm15, (arguments_scratch_area_size + 9 * 10h)
src/coreclr/nativeaot/Runtime/amd64/ExceptionHandling.asm:328: movdqa xmm15, [rsp + arguments_scratch_area_size + 9 * 10h]
src/coreclr/nativeaot/Runtime/amd64/ExceptionHandling.asm:425: movdqa xmm15,[r8 + OFFSETOF__REGDISPLAY__Xmm + 9*10h]
src/coreclr/nativeaot/Runtime/amd64/ExceptionHandling.asm:578: movdqa xmm15,[rdx + OFFSETOF__REGDISPLAY__Xmm + 9*10h]
src/coreclr/nativeaot/Runtime/amd64/ExceptionHandling.asm:635: movdqa [rdx + OFFSETOF__REGDISPLAY__Xmm + 9*10h], xmm15
src/coreclr/nativeaot/Runtime/inc/gcinfo.h:913: // any subset of xmm6-xmm15 may be saved, but no registers in xmm0-xmm5 should be present
src/coreclr/nativeaot/Runtime/regdisplay.h:35: Fp128 Xmm[16-6]; // preserved xmm6..xmm15 regs for EH stackwalk
Various PAL and VM locations (cc. @jkotas):
src/coreclr/pal/inc/pal.h:1666: M128A Xmm15;
src/coreclr/pal/inc/pal.h:1787: PM128A Xmm15;
src/coreclr/pal/prebuilt/inc/cordebug.h:9079: REGISTER_AMD64_XMM15 = ( REGISTER_AMD64_XMM14 + 1 ) ,
src/coreclr/pal/src/arch/amd64/asmconstants.h:80:#define CONTEXT_Xmm15 CONTEXT_Xmm14+16
src/coreclr/vm/amd64/AsmHelpers.asm:308: save_xmm128_frame xmm15, rbp, OFFSETOF__CONTEXT__Xmm15
src/coreclr/vm/amd64/AsmHelpers.asm:380: movdqa xmm15, [rbp+OFFSETOF__CONTEXT__Xmm15]
src/coreclr/vm/amd64/asmconstants.h:440:#define OFFSETOF__CONTEXT__Xmm15 (8*6 + 4*2 + 2*6 + 4 + 8*6 + 8*16 + 8 + 2*16 + 8*16 + 16*15)
src/coreclr/vm/amd64/asmconstants.h:441:ASMCONSTANTS_C_ASSERT(OFFSETOF__CONTEXT__Xmm15
src/coreclr/vm/amd64/asmconstants.h:442: == offsetof(CONTEXT, Xmm15));
src/coreclr/vm/i386/stublinkerx86.h:78: kXMM15 = 15,